Semiconductor devices having different package sizes made by using common parts

专利摘要:
A semiconductor device having a semiconductor element and a plurality of segments formed by dividing a conductive plate. Some of the segments are electrically coupled with electrodes of said semiconductor element and constitute lead pad portions as mounting electrodes of the semiconductor device. Other segments among the plurality of divided segments constitute die pad portions on which the semiconductor element is mounted. The plurality of divided segments and the semiconductor element are sealed and supported together by a resin material portion. The resin material portion fills the space between the divided segments as the lead pad portions. Semiconductor devices having various package sizes can be fabricated by using standardized common parts.
公开号:US20010009301A1
申请号:US09/767,761
申请日:2001-01-23
公开日:2001-07-26
发明作者:Kosuke Azuma
申请人:NEC Corp；
IPC主号:H01L24-16

专利说明:
[0001] The present invention relates generally to a surface mount type semiconductor device having a lead-less structure, and more particularly to a semiconductor device and a method of manufacturing the same in which common parts can be used among semiconductor devices having different package sizes. [0001] BACKGROUND OF THE INVENTION
[0002] Recently, packages of components such as semiconductor integrated circuits, transistors, diodes and the like are downsized and made thin. In such components, existence of connecting leads gives large influence on the package size. Therefore, there is proposed a surface mount type semiconductor device having a lead-less structure in which connecting leads are not used. Especially, in a semiconductor integrated circuit device, it is required that a disposition pitch of connecting leads of a lead frame is minute, in order to realize a device having many lead pins. Also, width or thickness of each lead must be reduced and there is a possibility that the leads bend easily, causing short circuit between the leads. Alternatively, it is required that the package size is enlarged to realize a large disposition pitch of the leads. [0002]
[0003] Japanese patent laid-open publication No. 9-162348 discloses a semiconductor device having such lead-less structure. FIG. 40 is a cross sectional view of the semiconductor device disclosed in Japanese patent laid-open publication No. 9-162348. As shown in FIG. 40, a semiconductor element (element chip) [0003] 303 is fixed onto an element fixing resin board 301, and the upper side and peripheral area of the semiconductor element 303 are molded by package resin 305. Also, there are provided a plurality of projected portions 307 on the bottom surface of the package resin 305. The surface of each of the projected portions 307 is coated by a metal film 309. The metal films 309 are electrically coupled with the semiconductor element 303 via bonding wires 311, within the package resin 305. Thereby, the metal films 309 function as mounting electrodes for mounting the semiconductor device onto a printed circuit board and the like. Thus, in the semiconductor device shown in FIG. 40, mounting electrodes are formed directly on the bottom surface of the package, and it is not necessary to use a lead-frame. Therefore, it is possible to avoid the above-mentioned disadvantages caused by the lead-frame. Also, the package is effectively downsized and made thin.
[0004] Japanese patent laid-open publication No. 9-252014 discloses another semiconductor device of this type. FIG. 41 is a cross sectional view of a semiconductor device disclosed in Japanese patent laid-open publication No. 9-252014. The semiconductor device of FIG. 41 is fabricated as follows. First, a metal foil is shaped into predetermined patterns to form a die pad portion [0004] 401 and a plurality of electrode portions 403. On the die pad portion 401, a semiconductor element 405 is mounted by using mounting material 407. The electrode portions 403 are then electrically coupled with the semiconductor element 405 by using bonding wires 409. Thereafter, the semiconductor element 405 and the bonding wires 409 are molded by package resin 411. In the semiconductor device shown in FIG. 41, the electrode portions 403 are exposed at the bottom surface of the package resin 411. Thereby, it is possible to realize a surface mount type semiconductor device having a lead-less structure. Thus, it is possible to downsize and thin down the package. In Japanese patent laid-open publication No. 9-252014, a method is also disclosed in which, before patterning a metal foil, a semiconductor element is mounted on the metal foil and wire bonding is performed, and thereafter the metal foil is patterned into desired patterns. Also, Japanese patent laid-open publication No. 10-22440 discloses a technology similar to that described above.
[0005] Further, there is known a technology disclosed in Japanese patent laid-open publication No. 8-115989 and Japanese patent laid-open publication No. 8-115991. FIG. 42 is a cross sectional view of a semiconductor device disclosed in Japanese patent laid-open publication No. 8-115989 and Japanese patent laid-open publication No. 8-115991. The semiconductor device shown in FIG. 42 has a frame-like terminal portion [0005] 501, and a plurality of column-like terminal portions 503 which are disposed within the frame-like terminal portion 501 and which are insulated from each other and from the frame-like terminal portion 501 via resin portion 505. A semiconductor element 509 is disposed on a patterned layer 507 formed on the frame-like terminal portion 501 and the column-like terminal portions 503. The semiconductor element 509 is electrically coupled with the patterned layer 507 via bonding wires 511. Thereby, the semiconductor element 509 is electrically coupled with the column-like terminal portions 503 via conducting pattern portions of the patterned layer 507. Further, the semiconductor element 509, the bonding wires 511 and the like are molded by resin 513. In this semiconductor device, the column-like terminal portions 503 are disposed in an area just under the semiconductor element 509 as electrodes for mounting. Therefore, it is possible to realize a semiconductor device having a grid array structure.
[0006] In each of the conventional semiconductor devices mentioned above, a relatively large number of fabrication steps are required and fabrication process becomes complicated, thereby manufacturing costs are increased. That is, in the semiconductor device shown in FIG. 40, it is necessary to provide the projected portions [0006] 307 at the bottom surface of the package resin 305, and to form the metal film 309 on the surface of the projected portions 307. The method of manufacturing such semiconductor device disclosed in Japanese patent laid-open publication No. 9-162348 is as follows. First, a metal base member is formed in which recessed portions are provided at portions corresponding to the projected portions 307. The metal film 309 is then selectively formed in each of the recessed portions. Then, mounting of the semiconductor element 303 and electrical connection between the semiconductor element 303 and the metal film 309 via bonding wires 311 are performed. Thereafter, molding by the package resin 305 is performed. The metal base member is finally removed to fabricate the semiconductor device. In this method, number of processes for selectively forming the metal film 309 is relatively large, and it is necessary to use the metal base member which becomes unnecessary after the completion of manufacturing. Therefore, manufacturing cost of the semiconductor device becomes large.
[0007] In the semiconductor device shown in FIG. 41, an etching process is required to pattern a metal foil into desired patterns when the die pad portions [0007] 401 and the electrode portions 403 are formed. Therefore, manufacturing process becomes complicated. Also, it is necessary to use a base member for supporting the metal foil when the metal foil is patterned. Since this base member becomes unnecessary after manufacturing the semiconductor device, it causes an increase in the manufacturing cost of the semiconductor device, as in the semiconductor device shown in FIG. 40. When the metal foil is patterned after packaging the semiconductor element, the base member becomes unnecessary. However, since the etching process is performed by wet etching, it is necessary to perform water-resistant protection of the package when the etching is performed. Therefore, manufacturing process becomes complicated and, in this respect, manufacturing costs of the semiconductor device become large.
[0008] Further, in the semiconductor device shown in FIG. 42, the pattern layer [0008] 507 is required between the frame-like terminal portion and the column-like terminal portions 501 and 503 and the semiconductor element 509 mounted thereon for selectively and electrically coupling the bonding wires 511 with the column-like terminal portions 503. Therefore, a large number of components are required and manufacturing costs of the semiconductor device become large. Also, number of manufacturing processes increases and manufacturing process becomes complicated.
[0009] Also, the above-mentioned conventional semiconductor devices have common problems as follows. In order to fabricate the above-mentioned semiconductor devices, components such as the metal film portions [0009] 309, the electrode portions 403 each made of a metal foil, the column-like terminal portions 503, the pattern layer 507 and the like are required as mounting terminals. It is necessary that these components are previously designed and manufactured into predetermined electrode arrangement patterns and sizes in compliance with kinds and sizes of the semiconductor elements 303, 405 and 509. Therefore, when a semiconductor element having different kind or size is to be mounted, it is necessary to again design and fabricate the above-mentioned components having different patterns and sizes. Also, when the components are to be previously fabricated and prepared, it is necessary to prepare a plurality kinds of components applicable to a plurality kinds or sizes of semiconductor elements. Therefore, manufacturing and management of the components used for fabricating the semiconductor devices become complicated. SUMMARY OF THE INVENTION
[0010] Therefore, it is an object of the present invention to provide a surface mount type semiconductor device having a lead-less structure and a method of manufacturing the same in which the above-mentioned disadvantages of the prior art technology can be obviated. [0010]
[0011] It is another object of the present invention to provide a surface mount type semiconductor device having a lead-less structure and a method of manufacturing the same in which a simplified structure of the semiconductor device and a simplified manufacturing process thereof can be realized. [0011]
[0012] It is still another object of the present invention to provide a surface mount type semiconductor device having a lead-less structure and a method of manufacturing the same in which common parts can be utilized for making the semiconductor devices having different kinds and sizes. [0012]
[0013] According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor element; a plurality of divided segments formed by dividing a conductive plate, at least one of the divided segments being electrically coupled with an electrode of the semiconductor element; and a resin material portion supporting the plurality of divided segments and the semiconductor element together. [0013]
[0014] In this case, it is preferable that the at least one of the segments electrically coupled with the electrodes of the semiconductor element constitute lead pad portions as mounting electrodes, and at least one of other segments among the plurality of segments constitute die pad portions on which the semiconductor element is mounted. [0014]
[0015] It is also preferable that, among the plurality of segments, at least one of the segments located under the semiconductor element constitute die pad portions, and at least one of the segments which are disposed in the peripheral portion of the segments constituting the die pad portions and which are electrically coupled with the electrodes of the semiconductor element via bonding wires constitute lead pad portions. [0015]
[0016] It is further preferable that the resin material portion seals the semiconductor element and the bonding wires, and fills the space between the segments as the lead pad portions among the plurality of segments. [0016]
[0017] It is advantageous that the semiconductor element is mounted on the at least one of the segments as die pad portions via mounting material or tape-like adhesive. [0017]
[0018] It is also advantageous that a part of the segments located under the semiconductor element constitute die pad portions, and other part of the segments located under the semiconductor element are electrically coupled with electrodes of the semiconductor element via bumps and constitute lead pad portions. [0018]
[0019] It is further advantageous that the resin material portion seals the semiconductor element, and fills the space between the semiconductor element and the segments located under the semiconductor element and the space between the segments located under the semiconductor element. [0019]
[0020] It is preferable that the plurality of segments are formed by dividing a conductive plate into a lattice-like arrangement. [0020]
[0021] It is also preferable that each of the segments has a crank-like cross section in the direction of thickness of the conductive plate. [0021]
[0022] It is further preferable that the plurality of segments are disposed around the semiconductor element but are not disposed under the semiconductor element, at least one of the segments are electrically coupled with electrodes of the semiconductor element via bonding wires and constitute lead pad portions as mounting electrodes, and the resin material portion seals the semiconductor element and the bonding wires and fills the space between respective segments of the plurality of segments. [0022]
[0023] It is advantageous that the semiconductor element is a semiconductor integrated circuit chip, and electrodes of the semiconductor integrated circuit chip are respectively coupled with the segments as lead pad portions among the plurality of segments. [0023]
[0024] It is also advantageous that the semiconductor element is a diode chip, the diode chip is mounted on one of the plurality of segments, and an electrode of the diode chip is electrically coupled with other one of the segments adjacent the divided segment on which the diode chip is mounted. [0024]
[0025] It is further advantageous that the semiconductor element is a transistor chip, the transistor chip is mounted on one of the plurality of segments, and electrodes of the transistor chip are electrically coupled with two of the segments adjacent the divided segment on which the transistor chip is mounted. [0025]
[0026] It is preferable that a ball-like electrode is formed on the backside surface of the at least one of the segments constituting said lead pad portions. [0026]
[0027] It is also preferable that the bumps are solder bumps or studbumps. [0027]
[0028] It is further preferable that a resist film is formed on the backside surface of the at least one of the segments constituting said die pad portions. [0028]
[0029] It is advantageous that an outer dimension of a group of the segments which constitute the die pad portions and the lead pad portions is larger than an outer dimension of the semiconductor element. [0029]
[0030] It is also advantageous that an outer dimension of a group of the segments which constitute the die pad portions and the lead pad portions is substantially equal to an outer dimension of the semiconductor element. [0030]
[0031] According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a conductive plate; forming concave trenches in the conductive plate to form a plurality of segments; preparing a semiconductor element; mounting a semiconductor element on the conductive plate having the concave trenches formed therein; disposing resin material on the conductive plate wherein a part of the resin material enters at least a part of the concave trenches; and removing the backside portion of the conductive plate so as to expose bottom portions of the concave trenches. [0031]
[0032] In this case, it is preferable that, in the removing the backside of the conductive plate, the backside of the conductive plate is polished or etched so as to expose bottom portions of the concave trenches. [0032]
[0033] It is also preferable that, in the mounting a semiconductor element on the conductive plate, the semiconductor element is mounted on at least one of the segments; wherein the method further comprises electrically coupling electrodes of the semiconductor element with segments disposed around the at least one of the segments on which the semiconductor element is mounted; and wherein, in the disposing the resin material on the conductive plate, the semiconductor element and the bonding wires are sealed by the resin material, and the resin material fills the concave trenches between segments disposed around the at least one of the segments on which the semiconductor element is mounted. [0033]
[0034] It is further preferable that, in the preparing a semiconductor element, a semiconductor element having bumps formed thereon is prepared; wherein, in the mounting the semiconductor element on the conductive plate, electrodes of the semiconductor element are electrically coupled with at least one of segments disposed under the semiconductor element via the bumps; and wherein, in the disposing the resin material on the conductive plate, the semiconductor element is sealed by the resin material, and the resin material fills a space between the semiconductor element and the conductive plate. [0034]
[0035] It is advantageous that, in the forming concave trenches in the conductive plate to form a plurality of segments, the concave trenches are formed in lattice-like arrangement. [0035]
[0036] It is also advantageous that, in the forming concave trenches in the conductive plate to form a plurality of segments, the concave trenches are formed by using a technology selected from a group consisting of half-cut dicing, half-etching and press working. [0036]
[0037] It is further advantageous that, in the mounting a semiconductor element on the conductive plate, the semiconductor element is mounted on the conductive plate via mounting material or tape-like adhesive. [0037]
[0038] It is preferable that the method further comprises caving a portion of the conductive plate to form a concave portion, before the mounting a semiconductor element on the conductive plate; wherein, in the mounting a semiconductor element on the conductive plate, the semiconductor element is mounted in the concave portion via mounting material; wherein the method further comprises electrically coupling electrodes of the semiconductor element with segments disposed around the concave portion via bonding wires; wherein, in the disposing the resin material on the conductive plate, the semiconductor element and the bonding wires are sealed by the resin material, and the resin material fills the concave trenches between segments disposed around the concave portion; and wherein, in the removing the backside portion of the conductive plate, the mounting material is exposed. [0038]
[0039] It is also preferable that the semiconductor element is a semiconductor integrated circuit chip. [0039]
[0040] It is further preferable that the semiconductor element is a diode chip; wherein, in the mounting the semiconductor element on the conductive plate, the diode chip is mounted on one of the plurality of segments; wherein the method further comprises electrically coupling an electrode of the diode chip with one of the segments adjacent the divided segment on which the diode chip is mounted via a bonding wire; and wherein, in the disposing the resin material on the conductive plate, the diode chip and the bonding wire are sealed by the resin material, and the resin material fills the concave trench between the divided segment electrically coupled with the electrode of the diode chip and the divided segment on which the diode chip is mounted. [0040]
[0041] It is advantageous that the semiconductor element is a transistor chip; wherein, in the mounting the semiconductor element on the conductive plate, the transistor chip is mounted on one of the plurality of segments; wherein the method further comprises electrically coupling electrodes of the transistor chip with two of the segments adjacent the divided segment on which the transistor chip is mounted via bonding wires; and wherein, in the disposing the resin material on the conductive plate, the transistor chip and the bonding wires are sealed by the resin material, and the resin material fills the concave trenches between the segments electrically coupled with the electrodes of the transistor chip and the divided segment on which the transistor chip is mounted. [0041]
[0042] It is also advantageous that, in the disposing the resin material on the conductive plate, the resin material is disposed by using a technology selected from a group consisting of molding by a metal die, coating, and potting. [0042]
[0043] It is further advantageous that, in the preparing a semiconductor element, a plurality of semiconductor elements are prepared; wherein, in the mounting the semiconductor element on the conductive plate, the plurality of semiconductor elements are mounted on the conductive plate; and wherein, in the disposing the resin material on the conductive plate, the plurality of semiconductor elements are sealed by the resin material. [0043]
[0044] It is preferable that the method further comprises, after removing the backside portion of the conductive plate, cutting the resin material in predetermined locations to form separate semiconductor devices each including at least one semiconductor element. [0044]
[0045] It is also preferable that, in the forming concave trenches in the conductive plate to form a plurality of segments, the concave trenches are formed in lattice-like arrangement; wherein, in the preparing a semiconductor element, a semiconductor wafer on which a plurality of semiconductor elements are formed is prepared; wherein, in the mounting the semiconductor element on the conductive plate, the semiconductor wafer is mounted on the conductive plate and electrodes of each semiconductor element formed in the semiconductor wafer are electrically coupled with corresponding segments of the plurality of segments via bumps; wherein, in the disposing the resin material on the conductive plate, the resin material fills a space between the semiconductor wafer and the conductive plate; and wherein the method further comprises, after removing the backside portion of the conductive plate, cutting the semiconductor wafer and the resin material in predetermined locations to form separate semiconductor devices each including at least one semiconductor element. [0045]
[0046] According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a conductive plate; preparing a supporting sheet; sticking the conductive plate on the supporting sheet; cutting the conductive plate stuck on the supporting sheet to form a plurality of segments supported by the supporting sheet; preparing a semiconductor element; mounting a semiconductor element on at least one of the plurality of segments; and disposing resin material on the plurality of segments, wherein a part of the resin material enters at least a part of spaces between the segments. [0046]
[0047] In this case, it is preferable that the method further comprises peeling the supporting sheet, after disposing the resin material. [0047]
[0048] It is also preferable that the supporting sheet has opening portions at predetermined locations, and is made of material which does not adhere to solder; and wherein, in the cutting the conductive plate stuck on the supporting sheet to form a plurality of segments supported by the supporting sheet, at least one of the segments is exposed via the opening portions of the supporting sheet. [0048]
[0049] It is further preferable that the method further comprises electrically coupling electrodes of the semiconductor element with segments disposed around the at least one of the segments on which the semiconductor element is mounted via bonding wires; and wherein, in the disposing the resin material, the semiconductor element and the bonding wires are sealed by the resin material, and the resin material fills spaces between segments disposed around the at least one of the segments on which the semiconductor element is mounted. [0049]
[0050] It is advantageous that, in the preparing a semiconductor element, a semiconductor element having electrodes on which bumps are formed is prepared; wherein, in the mounting a semiconductor element on at least one of the plurality of segments, electrodes of the semiconductor element are electrically coupled with at least one of the segments located under the semiconductor element via the bumps; and wherein, in the disposing the resin material, the semiconductor element is sealed by the resin material, and the resin material fills spaces between segments disposed under the semiconductor element and spaces between the semiconductor element and the segments located under the semiconductor element. [0050]
[0051] It is also advantageous that, in the cutting the conductive plate stuck on the supporting sheet to form a plurality of segments supported by the supporting sheet, the conductive plate is cut into lattice-like arrangement, and the supporting sheet is not cut substantially. [0051]
[0052] It is further advantageous that, in the mounting a semiconductor element on at least one of the segments, the semiconductor element is mounted on the at least one of the segments via mounting material or tape-like adhesive. [0052]
[0053] It is preferable that the semiconductor element is a semiconductor integrated circuit chip. [0053]
[0054] It is also preferable that the semiconductor element is a diode chip; wherein, in the mounting the semiconductor element on at least one of the segments, the diode chip is mounted on one of the plurality of segments; wherein the method further comprises electrically coupling an electrode of the diode chip with one of the segments adjacent the divided segment on which the diode chip is mounted via a bonding wire; and wherein, in the disposing the resin material, the diode chip and the bonding wire are sealed by the resin material, and the resin material fills a space between the divided segment electrically coupled with the electrode of the diode chip and the divided segment on which the diode chip is mounted. [0054]
[0055] It is further preferable that the semiconductor element is a transistor chip; wherein, in the mounting the semiconductor element on at least one of the segments, the transistor chip is mounted on one of the plurality of segments; wherein the method further comprises electrically coupling electrodes of the transistor chip with two of the segments adjacent the divided segment on which the transistor chip is mounted via bonding wires; and wherein, in the disposing the resin material, the transistor chip and the bonding wires are sealed by the resin material, and the resin material fills spaces between the segments electrically coupled with the electrodes of the transistor chip and the divided segment on which the transistor chip is mounted. [0055]
[0056] It is advantageous that, in the disposing the resin material, the resin material is disposed by using a technology selected from a group consisting of molding by a metal die, coating, and potting. [0056]
[0057] It is also advantageous that, in the preparing a semiconductor element, a plurality of semiconductor elements are prepared; wherein, in the mounting the semiconductor element on at least one of the segments, the plurality of semiconductor elements are mounted on the segments; and wherein, in the disposing the resin material, the plurality of semiconductor elements are sealed by the resin material. [0057]
[0058] It is further advantageous that, in the cutting the conductive plate stuck on the supporting sheet to form a plurality of segments supported by the supporting sheet, the conductive plate is cut into lattice-like arrangement; wherein, in the preparing a semiconductor element, a semiconductor wafer on which a plurality of semiconductor elements are formed is prepared; wherein, in the mounting a semiconductor element on at least one of the plurality of segments, the semiconductor wafer is mounted on the plurality of segments supported by the supporting sheet, and electrodes of each semiconductor element formed on the semiconductor wafer are electrically coupled with corresponding segments of the plurality of segments via bumps; wherein, in the disposing resin material, the resin material fills a space between the semiconductor wafer and a plurality of segments supported by the supporting sheet and spaces between respective segments of the plurality of segments; and wherein the method further comprises cutting the semiconductor wafer and the resin material in predetermined locations to form separate semiconductor devices each including at least one semiconductor element. [0058]
[0059] According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a semiconductor element having electrodes on which bumps are formed; preparing a conductive plate; forming a first set of concave trenches in a lattice-like arrangement on the face side of the conductive plate; forming a second set of concave trenches in a lattice-like arrangement on the backside of the conductive plate, the second set of concave trenches are shifted from the first set of concave trenches in the direction along the surface of the conductive plate; mounting the semiconductor element on the face surface of the conductive plate, wherein electrodes of the semiconductor element are electrically coupled with segments divided by the first set of concave trenches via bumps; filling a space between the semiconductor element and the conductive plate with resin material; and cutting the conductive plate at locations shifted in the directions along the surface of the conductive plate from the first and second sets of concave trenches. [0059]
[0060] In this case, it is preferable that, in the preparing a semiconductor element having electrodes on which bumps are formed, a semiconductor wafer on which a plurality of semiconductor elements are formed thereon is prepared, and each of the semiconductor element has electrodes on which bumps are formed; wherein, in the mounting the semiconductor element on the face surface of the conductive plate, the semiconductor wafer is mounted on the face surface of the conductive plate, and electrodes of each of the semiconductor elements are electrically coupled with segments divided by the first set of concave trenches via bumps; wherein, in the filling a space between the semiconductor element and the conductive plate with resin material, the resin material fill a space between the semiconductor wafer and the conductive plate; and wherein the method further comprises cutting the semiconductor wafer and the resin material in predetermined locations to form separate semiconductor devices each including at least one semiconductor element. [0060]
[0061] It is also preferable that the forming a second set of concave trenches in a lattice-like arrangement on the backside of the conductive plate is performed after filling a space between the semiconductor element and the conductive plate with resin material; wherein, in the forming a second set of concave trenches in a lattice-like arrangement on the backside of the conductive plate, the second set of concave trenches partially overlap the first set of the concave trenches and the conductive plate is separated by the first and second sets of concave trenches; and thereby obviating the cutting the conductive plate at locations shifted in the directions along the surface of the conductive plate from the first and second sets of concave trenches. [0061]
[0062] It is further preferable that, in the forming a first set of concave trenches in a lattice-like arrangement on the face side of the conductive plate and in the forming a second set of concave trenches in a lattice-like arrangement on the backside of the conductive plate, the first and second sets of concave trenches are formed by using a technology selected from a group consisting of half-cut dicing, half-etching and press working. [0062]
[0063] As mentioned above, in a semiconductor device according to the present invention, a plurality of segments or divided segments are formed from a conductor plate or board, and lead pad portions are constituted of the segments which are electrically coupled with electrodes of a semiconductor element. Therefore, by appropriately determining which divided segments are used as lead pad portions depending on the size and kind of each of the semiconductor elements, it is possible to commonly utilize the divided segments for the semiconductor elements having different sizes and kinds to form device packages. Also, it is possible to form die pad portions by using portions of the divided segments and to mount a semiconductor element on the die pad portions. In this case, other portions of the divided segments are used as lead pad portions and electrodes of the semiconductor element are electrically coupled with the lead pad portions. Alternatively, it is possible to electrically couple bumps provided on electrodes of a semiconductor element with divided segments to form lead pad portions. Thereby, it is possible to mount or dispose a semiconductor element in face-up condition or in face-down condition. The lead pad portions may be disposed in the periphery of the package, or may be disposed in the bottom portion of the package in lattice-like arrangement. The same standard conducting plate can be utilized to fabricate surface-mount type semiconductor devices having lead-less structure, even if the semiconductor devices have different sizes and/or kinds. [0063]
[0064] In the method of manufacturing a semiconductor device according to the present invention, segments or divided segments are defined by forming concave trenches in a conductor plate. A semiconductor element is mounted on the divided segments, and the semiconductor element and the divided segments are electrically coupled. Thereafter, the backside portion of the conductor plate is removed to form individual divided segments. Therefore, it is possible to easily perform a process of mounting a semiconductor element, a process of electrical connection between the semiconductor element and the divided segments, and a process of forming a package resin portion. Also, it is possible to fabricate a semiconductor device which has a plurality of lead pad portions finally insulated from each other. Therefore, according to the present invention, the number of parts and the number of process steps do not increase uselessly, and manufacturing process can be simplified. [0064] BRIEF DESCRIPTION OF THE DRAWINGS
[0065] These and other features, and advantages, of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals designate identical or corresponding parts throughout the figures, and in which: [0065]
[0066] FIG. 1 is an outside perspective view of a semiconductor device according to a first embodiment of the present invention wherein a part of the semiconductor device is cut away; [0066]
[0067] FIG. 2A is a plan view schematically showing an internal structure of the semiconductor device of FIG. 1; [0067]
[0068] FIG. 2B is a cross sectional view of the semiconductor device of FIG. 1; [0068]
[0069] FIG. 3A is a cross sectional view showing a condition in which the semiconductor device of FIG. 1 is mounted on a mounting substrate; [0069]
[0070] FIG. 3B is a cross sectional view showing another condition in which the semiconductor device of FIG. 1 is mounted on a mounting substrate; [0070]
[0071] FIG. 4A is a top plan view illustrating a method of manufacturing a semiconductor device according to the first embodiment in a first manufacturing step; [0071]
[0072] FIG. 4B is a cross sectional view taken along the center line portion of the workpiece of FIG. 4A illustrating a method of manufacturing a semiconductor device according to the first embodiment in the first manufacturing step; [0072]
[0073] FIG. 5A is a top plan view illustrating a method of manufacturing a semiconductor device according to the first embodiment in a second manufacturing step; [0073]
[0074] FIG. 5B is a cross sectional view taken along the center line portion of the workpiece of FIG. 5A illustrating a method of manufacturing a semiconductor device according to the first embodiment in the second manufacturing step; [0074]
[0075] FIG. 6A is a top plan view illustrating a method of manufacturing a semiconductor device according to the first embodiment in a third manufacturing step; [0075]
[0076] FIG. 6B is a cross sectional view taken along the center line portion of the workpiece of FIG. 6A illustrating a method of manufacturing a semiconductor device according to the first embodiment in the third manufacturing step; [0076]
[0077] FIG. 7A is a top plan view illustrating a method of manufacturing a semiconductor device according to the first embodiment in a fourth manufacturing step; [0077]
[0078] FIG. 7B is a cross sectional view taken along the center line portion of the workpiece of FIG. 7A illustrating a method of manufacturing a semiconductor device according to the first embodiment in the fourth manufacturing step; [0078]
[0079] FIG. 8A is a top plan view illustrating a method of manufacturing a semiconductor device according to the first embodiment in a fifth manufacturing step; [0079]
[0080] FIG. 8B is a cross sectional view taken along the center line portion of the workpiece of FIG. 8A illustrating a method of manufacturing a semiconductor device according to the first embodiment in the fifth manufacturing step; [0080]
[0081] FIG. 9A is a top plan view illustrating a method of manufacturing a semiconductor device according to the first embodiment in a sixth manufacturing step; [0081]
[0082] FIG. 9B is a cross sectional view taken along the center line portion of the workpiece of FIG. 9A illustrating a method of manufacturing a semiconductor device according to the first embodiment in the sixth manufacturing step; [0082]
[0083] FIG. 10A is a cross sectional view of a semiconductor device in which a semiconductor element shown in FIG. 1 is mounted; [0083]
[0084] FIG. 10B is a cross sectional view of a semiconductor device in which a semiconductor element having a size larger than that of the semiconductor element of FIG. 1 is mounted; [0084]
[0085] FIG. 11A is a top plan view illustrating a condition of a semiconductor device during manufacture as a first variation of the first embodiment; [0085]
[0086] FIG. 11B is a cross sectional view illustrating a condition of a semiconductor device during manufacture as the first variation of the first embodiment; [0086]
[0087] FIG. 12A is a partially cutaway top plan view illustrating another condition of a semiconductor device during manufacture as the first variation of the first embodiment; [0087]
[0088] FIG. 12B is a cross sectional view illustrating another condition of a semiconductor device during manufacture as the first variation of the first embodiment; [0088]
[0089] FIG. 13A is a partially cutaway top plan view illustrating another condition of a semiconductor device during manufacture as a second variation of the first embodiment; [0089]
[0090] FIG. 13B is a cross sectional view illustrating another condition of a semiconductor device during manufacture as the second variation of the first embodiment; [0090]
[0091] FIG. 14A is a top plan view illustrating a method of manufacturing a semiconductor device according to a second embodiment in a first manufacturing step; [0091]
[0092] FIG. 14B is a cross sectional view taken along the center line portion of the workpiece of FIG. 14A illustrating a method of manufacturing a semiconductor device according to the second embodiment in the first manufacturing step; [0092]
[0093] FIG. 15 is a plan view showing a semiconductor element used in the first manufacturing step illustrated in FIG. 14A and FIG. 14B; [0093]
[0094] FIG. 16A is a top plan view illustrating a method of manufacturing a semiconductor device according to the second embodiment in a second manufacturing step; [0094]
[0095] FIG. 16B is a cross sectional view taken along the center line portion of the workpiece of FIG. 16A illustrating a method of manufacturing a semiconductor device according to the second embodiment in the second manufacturing step; [0095]
[0096] FIG. 17A is a top plan view illustrating a method of manufacturing a semiconductor device according to the second embodiment in a third manufacturing step; [0096]
[0097] FIG. 17B is a cross sectional view taken along the center line portion of the workpiece of FIG. 17A illustrating a method of manufacturing a semiconductor device according to the second embodiment in the third manufacturing step; [0097]
[0098] FIG. 18A is a top plan view illustrating a method of manufacturing a semiconductor device according to the second embodiment in the fourth manufacturing step; [0098]
[0099] FIG. 18B is a cross sectional view taken along the center line portion of the workpiece of FIG. 18A illustrating a method of manufacturing a semiconductor device according to the second embodiment in the fourth manufacturing step; [0099]
[0100] FIG. 19A is a perspective view showing a semiconductor wafer and illustrating a method of manufacturing a semiconductor device according to a third embodiment; [0100]
[0101] FIG. 19B is a perspective view showing a metal plate and illustrating a method of manufacturing a semiconductor device according to the third embodiment; [0101]
[0102] FIG. 20A is a cross sectional view illustrating a condition of workpiece during manufacture according to a method of manufacturing a semiconductor device of the third embodiment; [0102]
[0103] FIG. 20B is a cross sectional view illustrating another condition of workpiece during manufacture according to a method of manufacturing a semiconductor device of the third embodiment; [0103]
[0104] FIG. 20C is a cross sectional view illustrating still another condition of workpiece during manufacture according to a method of manufacturing a semiconductor device of the third embodiment; [0104]
[0105] FIG. 20D is a cross sectional view illustrating still another condition of workpiece during manufacture according to a method of manufacturing a semiconductor device of the third embodiment; [0105]
[0106] FIG. 21 is a partially enlarged perspective view showing a metal plate used in a method of manufacturing a semiconductor device according to a first variation of the third embodiment; [0106]
[0107] FIG. 22 is a schematic plan view showing a relationship between concave trenches in a metal plate used in a method of manufacturing a semiconductor device according to the first variation of the third embodiment; [0107]
[0108] FIG. 23A is a cross sectional view showing a method of manufacturing a semiconductor device by using the metal plate shown in FIG. 21 according to the first variation of the third embodiment; [0108]
[0109] FIG. 23B is a cross sectional view showing a method of manufacturing a semiconductor device by using the metal plate shown in FIG. 21 according to the first variation of the third embodiment; [0109]
[0110] FIG. 23C is a cross sectional view showing a method of manufacturing a semiconductor device by using the metal plate shown in FIG. 21 according to the first variation of the third embodiment; [0110]
[0111] FIG. 23D is a cross sectional view showing a method of manufacturing a semiconductor device by using the metal plate shown in FIG. 21 according to the first variation of the third embodiment; [0111]
[0112] FIG. 23E is a cross sectional view showing a method of manufacturing a semiconductor device by using the metal plate shown in FIG. 21 according to the first variation of the third embodiment; [0112]
[0113] FIG. 24 is a schematic plan view illustrating areas in which a photoresist mask is to be formed according to the first variation of the third embodiment; [0113]
[0114] FIG. 25 is a perspective view showing a divided segment made from a metal plate and illustrating a method of manufacturing a semiconductor device according to first variation of the third embodiment; [0114]
[0115] FIG. 26A is a cross sectional view showing a method of manufacturing a semiconductor device according to a second variation of the third embodiment; [0115]
[0116] FIG. 26B is a cross sectional view showing a method of manufacturing a semiconductor device according to the second variation of the third embodiment; [0116]
[0117] FIG. 27A is a top plan view illustrating a method of manufacturing a semiconductor device according to a fourth embodiment in a first manufacturing step; [0117]
[0118] FIG. 27B is a cross sectional view taken along the center line portion of the workpiece of FIG. 27A illustrating a method of manufacturing a semiconductor device according to the fourth embodiment in the first manufacturing step; [0118]
[0119] FIG. 28A is a top plan view illustrating a method of manufacturing a semiconductor device according to the fourth embodiment in a second manufacturing step; [0119]
[0120] FIG. 28B is a cross sectional view taken along the center line portion of the workpiece of FIG. 28A illustrating a method of manufacturing a semiconductor device according to the fourth embodiment in the second manufacturing step; [0120]
[0121] FIG. 29A is a cross sectional view illustrating a method of manufacturing a semiconductor device according to the fourth embodiment in a subsequent manufacturing step; [0121]
[0122] FIG. 29B is a cross sectional view illustrating a method of manufacturing a semiconductor device according to the fourth embodiment in a subsequent manufacturing step; [0122]
[0123] FIG. 29C is a cross sectional view illustrating a method of manufacturing a semiconductor device according to the fourth embodiment in a subsequent manufacturing step; [0123]
[0124] FIG. 29D is a cross sectional view illustrating a method of manufacturing a semiconductor device according to the fourth embodiment in a subsequent manufacturing step; [0124]
[0125] FIG. 30A is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to a variation of the fourth embodiment; [0125]
[0126] FIG. 30B is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the variation of the fourth embodiment; [0126]
[0127] FIG. 30C is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the variation of the fourth embodiment; [0127]
[0128] FIG. 30D is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the variation of the fourth embodiment; [0128]
[0129] FIG. 30E is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the variation of the fourth embodiment; [0129]
[0130] FIG. 30F is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the variation of the fourth embodiment; [0130]
[0131] FIG. 31 is a schematic plan view illustrating a resist sheet used in the method according to the variation of the fourth embodiment; [0131]
[0132] FIG. 32 is a schematic plan view illustrating a positional relationship between opening portions and divided segments in the method according to the variation of the fourth embodiment; [0132]
[0133] FIG. 33A is a top plan view illustrating a method of manufacturing a semiconductor device according to a fifth embodiment; [0133]
[0134] FIG. 33B is a cross sectional view taken along the center line portion of the workpiece of FIG. 33A illustrating a method of manufacturing a semiconductor device according to the fifth embodiment; [0134]
[0135] FIG. 34A is a top plan view illustrating a method of manufacturing a semiconductor device according to the fifth embodiment; [0135]
[0136] FIG. 34B is a cross sectional view taken along the center line portion of the workpiece of FIG. 34A illustrating a method of manufacturing a semiconductor device according to the fifth embodiment; [0136]
[0137] FIG. 35A is a top plan view illustrating a method of manufacturing a semiconductor device according to the fifth embodiment; [0137]
[0138] FIG. 35B is a cross sectional view taken along the center line portion of the workpiece of FIG. 35A illustrating a method of manufacturing a semiconductor device according to the fifth embodiment; [0138]
[0139] FIG. 36A is a top plan view illustrating a method of manufacturing a semiconductor device according to the fifth embodiment; [0139]
[0140] FIG. 36B is a cross sectional view taken along the center line portion of the workpiece of FIG. 36A illustrating a method of manufacturing a semiconductor device according to the fifth embodiment; [0140]
[0141] FIG. 37A is a top plan view illustrating a method of manufacturing a semiconductor device according to a sixth embodiment; [0141]
[0142] FIG. 37B is a cross sectional view taken along the center line portion of the workpiece of FIG. 37A illustrating a method of manufacturing a semiconductor device according to the sixth embodiment; [0142]
[0143] FIG. 38A is a top plan view illustrating a method of manufacturing a semiconductor device including a plurality of diode chips; [0143]
[0144] FIG. 38B is a cross sectional view taken along the center line portion of the workpiece of FIG. 38A illustrating a method of manufacturing a semiconductor device including a plurality of diode chips; [0144]
[0145] FIG. 39A is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the sixth embodiment; [0145]
[0146] FIG. 39B is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the sixth embodiment; [0146]
[0147] FIG. 39C is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the sixth embodiment; [0147]
[0148] FIG. 39D is a cross sectional view illustrating a condition of workpiece during manufacture in a method of manufacturing a semiconductor device according to the sixth embodiment; [0148]
[0149] FIG. 40 is a cross sectional view illustrating a first conventional semiconductor device; [0149]
[0150] FIG. 41 is a cross sectional view illustrating a second conventional semiconductor device; and [0150]
[0151] FIG. 42 is a cross sectional view illustrating a third conventional semiconductor device. [0151] DESCRIPTION OF A PREFERRED EMBODIMENT
[0152] With reference to the drawings, embodiments of the present invention will now be described in detail. FIG. 1 is an outside perspective view of a semiconductor device according to a first embodiment of the present invention wherein a part of the semiconductor device is cut away. FIG. 2A is a plan view schematically showing an internal structure of the semiconductor device of FIG. 1. FIG. 2B is a cross sectional view of the semiconductor device of FIG. 1 taken along the center line thereof. The semiconductor [0152] 1 device shown in these drawings comprises die pad portions 103, lead pad portions 105, a semiconductor element 107 such as a semiconductor integrated circuit chip, bonding wires 111, and package resin or a package resin portion 113. The die pad portions 103 and the lead pad portions 105 are formed from a conductive plate member, here a metal plate 101. The semiconductor element 107 is mounted on the die pad portions 103 via mounting material 109 made of silver paste and the like. The bonding wires 111 electrically couple between electrode pads 108 of the semiconductor element 107 and the lead pad portions 105. The packaging resin 113 covers and seals the semiconductor element 107 and the bonding wires 111. A part of the package resin 113 enters between the die pad portions 103 and the lead pad portions 105 and, thereby, the die pad portions 103 and the lead pad portions 105 are joined together.
[0153] Here, each of the die pad portions [0153] 103 and the lead pad portions 105 has a structure in which one board-like metal plate 101 is divided into square segments. Among the segments divided from the metal plate 101, a plurality of segments in the central area form the above-mentioned die pad portions 103. Also, a plurality of segments around the central area form the above-mentioned lead pad portions 105. In this embodiment, a resist film 115 made of an insulating material is formed on the backside surface of the die pad portions 103 such that the segments forming the die pad portions 103 are not exposed at the backside surface of the package.
[0154] FIG. 3A and FIG. 3B are cross sectional views each showing a condition in which the semiconductor device [0154] 1 having the above-mentioned structure is mounted on a mounting substrate 121. The mounting substrate shown in FIGS. 3A and 3B has a wiring circuit portion 123 made of a conductive film formed into predetermined patterns. As shown in FIG. 3A, the semiconductor device 1 can be mounted on the mounting substrate 121 as follows. That is, first, the semiconductor device 1 is placed on the mounting substrate 121. Then, solder portions 125 previously formed by a printing method and the like are reflowed by heating. Thereby, lead pad portions 105 as mounting electrodes of the semiconductor device 1 are soldered onto the wiring circuit portion 123. Alternatively, as shown in FIG. 3B, the semiconductor device 1 can be mounted on the mounting substrate 121 as follows. That is, first, on the bottom surface of lead pad portions 105, solder balls 127 are attached. The semiconductor device 1 and the solder balls 127 are pressed onto the wiring circuit 123 of the mounting substrate 121 while heating the solder balls 127 and the like. Thereby, the lead pad portions 105 of the semiconductor device 1 are coupled with the wiring circuit 123. When the solder balls 127 are used as shown in FIG. 3B, there is little possibility that the bottom surface of the die pad portions 103 contact the wiring circuit 123. Therefore, it is possible to omit the resist film 115.
[0155] An explanation will now be made on a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. [0155] 4A-9A and FIGS. 4B-9B are top or bottom plan views and cross sectional views taken along the center lines of the top or bottom plan views, illustrating a method of manufacturing a semiconductor device according to the first embodiment in order of manufacturing steps.
[0156] As shown in the top plan view of FIG. 4A and in the cross sectional view of FIG. 4B, there is prepared a metal plate [0156] 101 which has a rectangular shape, here a square shape, and which is made of copper, 42 alloy and the like. The metal plate 101 has a thickness of, for example, approximately 0.1-2 mm. Then, a plurality of concave trenches 131 are formed on the surface of the metal plate 101 in each of X direction and Y direction. The concave trenches 131 are formed, for example, by using a dicing saw and the like which are used for cutting a semiconductor wafer into separate chips. In this case, half-cut dicing is performed such that the concave trenches 131 are formed to a depth which is approximately a half of the thickness of the metal plate 101. Thereby, the surface portion of the metal plate 101 is zoned into squares or into a lattice-like arrangement. It is also possible to form the concave trenches 131 on the surface of the metal plate 101 by press working which uses a metal die. Further, it is possible to form the concave trenches 131 by etching which uses a photolithographic technology. Here, the width of each of the concave trenches 131 may vary depending on a type and the like of the semiconductor device. However, it is preferable that the width of each concave trench 131 is sufficiently large such that enough insulation between terminals can be obtained. Also, the sizes in lateral and longitudinal directions of each area between the concave trenches 131, that is, an individual piece in the lattice arrangement zoned or divided by the concave trenches 131 are determined by the wire-bondable pitch size, the size of external terminals, and the like. Here, the individual piece zoned by the concave trenches 131 is finally divided into a separate piece and, therefore, is referred to as a divided segment or a segment.
[0157] Next, as shown in the top plan view of FIG. 5A and in the cross sectional view of FIG. 5B, a semiconductor element [0157] 107 is mounted on the surface of the metal plate 101 via mounting material 109. As the mounting material 109, metal solder such as silver past and the like, conductive resin, and the like are used. The semiconductor element 107 is positioned such that the surface having electrodes 108 thereon faces toward upside, and the backside surface of the semiconductor element 107 is bonded onto the face surface of the metal plate 101, here the upper surfaces of a plurality of segments 133 divided by the concave trenches 131. In this case, the mounting material 109 enters and fills the concave trenches 131 in an area under the semiconductor element 107 mounted on the metal plate 101. Thereby, among the segments 133, the segments 133 a existing in an area under the semiconductor element 107 are joined together by the mounting material 109. These segments 133 a later form die pad portions 103.
[0158] Thereafter, as shown in the top plan view of FIG. 6A and in the cross sectional view of FIG. 6B, the electrodes [0158] 108 of the semiconductor element 107 and the upper surface portions of the segments 133 are respectively coupled by bonding wires 111. In this case, the segments 133 which are coupled with the electrodes 108 of the semiconductor element 107 are those not joined together by the mounting material 109. That is, among the segments 133, all or part of the segments 133 b which are disposed outside the above-mentioned segments 133 a are selected as the segments to be wire bonded. These segments 133 b later form lead pad portions 105.
[0159] As shown in the top plan view of FIG. 7A and in the cross sectional view of FIG. 7B, a package resin portion [0159] 113 is then formed. This is done, for example, as follows. First, the metal plate 101 is set in a metal mold for shaping resin not shown in the drawing, and the package resin portion 113 is formed by resin molding on the surface of the metal plate 101. Alternatively, resin is applied on the metal plate 101 to a predetermined thickness. Thereby, the package resin portion 113 is formed. Here, it should be noted that FIG. 7A is a partially cut away plan view. The semiconductor element 107 on the metal plate 101 and the bonding wires 111 are resin molded by the package resin 113. In this case, portion of the package resin 113 fills the concave trenches 131 which separate between the segments 133 a corresponding to the die pad portions 103 under the semiconductor element 107 and the segments 133 b corresponding to the lead pad portions 105 in the peripheral portion of the semiconductor element 107. Also, portion of the package resin 113 fills the concave trenches 131 which divide between the segments 133 b. Therefore, each of the segments 133 b corresponding to the lead pad portions 105 is joined to the adjacent segments 133 b, and to the segments 133 a corresponding to the die pad portions 103, via the insulating resin portion 113.
[0160] Then, as shown in the bottom plan view of FIG. 8A and in the cross sectional view of FIG. 8B, the bottom side of the metal plate [0160] 101 is polished away such that at least half of the thickness of the metal plate 101 is removed. This is done, for example, by mechanical polishing, or by chemical polishing such as etching and the like. By this polishing, the bottom portions of the concave trenches 131 of the metal plate 101 are also removed and, as a result, each of the segments 131 is formed as a piece completely zoned by the concave trenches 131. However, since, as mentioned above, the segments 131 are joined together by the mounting material 109 and the package resin portion 113, these segments are not separated from each other. Thereafter, as shown in FIGS. 2A and 2B, an insulating resist film 115 is selectively applied on an area where the segments 133 a corresponding to the die pad portions 103 exist, on the bottom surface of the semiconductor device 1. Alternatively, the resist film 115 may be formed by a printing method. Thereby, the bottom surface of the die pad portions 103 are coated by an insulator. It is also possible to apply the resist film 115 after a package separating process mentioned later. Further, if unnecessary, it is possible to omit forming the resist film 115. For the sake of easy understanding, the resist film 115 is not illustrated in FIGS. 8A and 8B.
[0161] As shown in the bottom plan view of FIG. 9A and in the cross sectional view of FIG. 9B, the package resin portion [0161] 113 is cut along the concave trenches 131 in the outside portions of the segments 133 b corresponding to the lead pad portions 105 by full-cut dicing. Thereby, the semiconductor device 1 is formed which has a rectangular outer shape and which has a plurality of lead pad portions 105 comprising a plurality of segments 133 b disposed along the periphery of the bottom surface of the semiconductor device 1. A conductive surface of each of the segments 133 b as the lead pad portions 105 is exposed in the periphery of the bottom surface of the semiconductor device 1. Therefore, the segments 133 b can function as mounting electrodes. In this way, the semiconductor device 1 shown in FIG. 1 is completed. In case the semiconductor device is a semiconductor device which requires a high heat dissipating effect at the die pad portions 103, for example, a semiconductor device in which a power semiconductor element is mounted, it is possible to use a structure in which the resist film 115 is not formed.
[0162] As mentioned above, in the semiconductor device according to the first embodiment, the semiconductor element [0162] 107 is mounted via the mounting material 109 on the metal plate 101 having the concave trenches 131 formed into a grid or lattice shape. The electrodes 108 of the semiconductor element 107 and the segments 133 b which are disposed in the periphery of the semiconductor element 107 and which are not joined by the mounting material 109 are then electrically coupled via the bonding wires 111. Then, molding by the package resin 113 is performed and thereby the semiconductor device 1 can be fabricated. In the metal plate 101, the concave trenches 131 are previously formed by half-cut dicing, and the metal plate 101 is divided into separate segments 133 after performing resin molding. Therefore, it is not necessary to use a base member for supporting a plurality of pad portions like the prior art method, and it is possible to decrease the number of components necessary to fabricate a semiconductor device. Also, in a polishing process of the metal plate 101 after the molding by the package resin 113, it is possible to adopt a mechanical polishing process, so that a manufacturing process does not become complicated. Further, a patterned layer required in the prior art for electrically coupling lead pad portions and electrodes of a semiconductor element is not required in the present embodiment. As a result, a structure of a semiconductor device becomes simple, and a manufacturing process thereof can also be simplified.
[0163] Also, in this embodiment, a plurality of segments [0163] 133 divided by the concave trenches 131 formed in the metal plate 101 are used as die pad portions 103 or as lead pad portions 105. In this respect, it is possible to freely select any segment 133 as a die pad portion 133 or a lead pad portion 105. Thus, it is possible, for example, to manufacture semiconductor devices from semiconductor elements having different sizes, i.e., different outer dimensions or from semiconductor elements having different number of electrodes, by using the same metal plate 101.
[0164] FIG. 10A and FIG. 10B are cross sectional views illustrating examples of such semiconductor devices. FIG. 10A shows a cross section of a semiconductor device [0164] 1 in which a semiconductor element 107 shown in FIG. 1 is mounted. FIG. 10B shows a cross section of a semiconductor device 1 a in which a semiconductor element 107 a having a size larger than that of the semiconductor element 107. Both the semiconductor devices 1 and 1 a can be fabricated by the same manufacturing process. That is, the semiconductor elements 107 and 107 a are mounted on the respective metal plates 101 having the same concave trenches 131. However, since the semiconductor element 107 and the semiconductor element 107 a have mutually different sizes, the number of divided segments 133 a joined together by the mounting material 109 under the semiconductor element 107 and the number of divided segments 133 a joined under the semiconductor element 107 a differ from each other. That is, the area of the semiconductor device 1 in which the die pad portions 103 exist differs from that of the semiconductor device 1 a. Also, corresponding to such difference, the number and locations of the divided segments 133 b disposed in the periphery of the semiconductor element 107 differ from those of the divided segments 133 b disposed in the periphery of the semiconductor element 107 a. That is, the number and/or locations of the lead pad portions 105 of the semiconductor device 1 differ from those of the lead pad portions 105 of the semiconductor device 1 a. In this condition, the molding process is performed by the package resin 113, and the package resin 113 is cut at the outer periphery of the lead pad portions 105. Thereby, the semiconductor device 1 and the semiconductor device 1 a having different package sizes are fabricated. The same kind of the metal plate 101 can be used for fabricating the semiconductor devices 1 and 1 a. Thus, it is possible to fabricate the semiconductor devices 1 and 1 a which have different sizes and which include semiconductor elements 107 and 107 a having different sizes, by using the same metal plate 101. Although not shown in the drawing, when a semiconductor element having different number and/or locations of the electrodes is to be mounted, the number of the divided segments 133 b used as lead pad portions 105 can be changes accordingly. It is also possible to change or select the divided segments 133 b to which the bonding wires are coupled. Thereby, it is possible to easily realize semiconductor devices which use various kind and/or sizes of semiconductor elements.
[0165] An explanation will now be made on a method of manufacturing a semiconductor device as variations of the first embodiment of the present invention. [0165]
[0166] FIG. 11A and FIG. 11B are a top plan view and a cross sectional view, respectively, illustrating a condition of a semiconductor device as a first variation during manufacture. FIG. 11A and FIG. 11B show a condition corresponding to that shown in FIG. 5A and FIG. 5B in the manufacturing process according to the first embodiment. The process steps performed before obtaining this condition are the same as those in the first embodiment, and explanation thereof is omitted here. [0166]
[0167] As shown in FIGS. 11A and 11B, in the method as a first variation of the first embodiment, when the semiconductor element [0167] 107 is mounted on a metal plate 101, a mounting tape 117 is used as mounting material. The mounting tape 117 is a double-faced adhesive tape. The lower surface of the mounting tape 117 is adhered to surfaces of the divided segments 133 formed in the metal plate 101. The upper surface of the mounting tape 117 is adhered to the backside of the semiconductor element 107. The process steps after this condition may be the same as those described with reference to FIGS. 6A and 6B in the first embodiment, and detailed description thereof is omitted here.
[0168] In the method according to the first variation of the first embodiment, the semiconductor element [0168] 107 can be mounted on the metal plate 101 by a simple process. That is, it is only necessary that the mounting tape 117 is adhered to a surface of the metal plate 101, and that the semiconductor element 107 is placed on the mounting tape 117. Therefore, in the first variation, when compared with the process of the first embodiment in which the mounting material 109 is applied onto the metal plate 101, it is possible to easily fabricate the semiconductor device. Here, the plurality of the divided segments 133 a constituting the die pad portions 103 just under the semiconductor element 107 are mutually joined by the mounting tape 117.
[0169] FIG. 12A and FIG. 12B are a partially cutaway top plan view and a cross sectional view, respectively, illustrating a condition of the semiconductor device according to the first variation corresponding to the above-mentioned condition shown in FIG. 7A and FIG. 7B. As shown in FIGS. 12A and 12B, when the molding by the package resin [0169] 113 is performed, it is preferable that portions of the package resin 113 enter into and fill the concave trenches 131 between the divided segments 133 a. Thereby, it is possible to enhance the strength of unifying the divided segments 133 a, i.e., the die pad portions 103 by the package resin 113.
[0170] An explanation will now be made on a method of manufacturing a semiconductor device as a second variation of the first embodiment of the present invention. FIG. 13A and FIG. 13B are a partially cutaway top plan view and a cross sectional view, respectively, illustrating a condition of a semiconductor device as the second variation during manufacture. FIG. 13A and FIG. 13B show a condition corresponding to that shown in FIG. 7A and FIG. 7B in the manufacturing process according to the first embodiment. In this variation, during a molding process by resin material, the package resin portion [0170] 113 a is formed by potting or dropping the resin material from just above the semiconductor element 107. The process steps performed before and after obtaining this condition are the same as those in the first embodiment, and explanation thereof is omitted here.
[0171] According to the second variation, it is possible to make the shape of the upper surface of the package resin portion [0171] 113 a into an arced surface or a spherical shape, or into a surface shape near the spherical shape, by the surface tension. Thus, it is possible to reduce the thickness of the package resin portion 113 a at the cutting portions. Therefore, when the package resin portion 113 a is cut into separate semiconductor devices, the quantity of the resin portion to be cut becomes very small and, therefore, it is possible to cut the package resin portion 113 a quite easily. Also, since there exists a resin material for the potting process which has a relatively low hardness when cured, it is also possible to cut the package resin portion 113 a into separate semiconductor devices by using a metal die. Therefore, it is possible to reduce cutting costs. Further, each of the semiconductor devices cut by this method does not have corner portions on the top surface thereof. Thus, probability of chipping or cracking of the package resin portion 113 a becomes small. As a result, it is possible to improve reliability of semiconductor devices.
[0172] Next, an explanation will be made on a method of manufacturing a semiconductor device according to the second embodiment of the present invention in order of manufacturing steps. First, in a manner similar to the process in the first embodiment shown in FIGS. 4A and 4B, grid shaped or lattice shaped concave trenches [0172] 131 are formed in a metal plate 101 by half-cut dicing and, thereby, divided segments 133 are formed. Then, as shown in a top plan view of FIG. 14A and in a cross sectional view of FIG. 14B, semiconductor element 107 b is mounted facedown on the metal plate 101. FIG. 15 is a plan view showing the face side surface, that is, the surface which is mounted on the metal plate 101, of the semiconductor element 107 b. On the face side surface of the semiconductor element 107 b, there are disposed electrodes 108 a along the peripheral portion thereof. Locations of the electrodes 108 a correspond to the divided segments 133 formed in the metal plate 101. That is, in this embodiment, the electrodes 108 a are disposed along the periphery of the semiconductor element 107 b in a pitch corresponding to that of the divided segments 133. On each of the electrodes 108 a, there is formed a ball-like bump 119 which is made of metal such as solder, gold and the like. The bumps 119 can also be formed by selective plating. The face surface of the semiconductor element 107 b is opposed to and pressed toward the metal plate 101 while heating the bumps 119 and the like, thereby the bumps 119 are respectively bonded to the surfaces of the corresponding divided segments 133. That is, the flip-chip bonding is performed. Therefore, each of the electrodes 108 a of the semiconductor element 107 b is electrically coupled with a corresponding one of the divided segments 133.
[0173] Thereafter, as shown in a partially cutaway plan view of FIG. 16A and in a cross sectional view of FIG. 16B, a package resin portion [0173] 113 b is formed. In the second embodiment, the molding by the package resin portion 113 b is performed such that portions of the package resin portion 113 b enter into and fill the concave trenches 131 between the divided segments 133 and the space between the semiconductor element 107 b and the metal plate 101. Thereafter, as shown in the bottom plan view of FIG. 17A and in the cross sectional view of FIG. 17B, the bottom side of the metal plate 101 is polished away such that the bottom portions of the concave trenches 131 of the metal plate 101 are removed. As a result, each of divided segments 133 is formed as a piece completely zoned by the concave trenches 131. In this case, since, as mentioned above, the divided segments 133 are joined together by the package resin portion 113 b, these divided segments are not separated from each other. Among the divided segments 133, the divided segments 133 bonded with the bumps 119 of the semiconductor element 107 b constitute lead pad portions 105, and function as mounting electrodes. The divided segments 133 which are located under the semiconductor element 107 b and which are not bonded with the bumps 119 constitute die pad portions 103 which are insulated from the lead pad portions 105 and which hold the semiconductor element 107 b. Thereafter, although not shown in the drawing, the package resin portion 113 b is cut along the concave trenches 131 in the outside portions of the segments 133 corresponding to the lead pad portions 105. Thereby, the semiconductor device 1 b is completed as shown in a bottom plan view of FIG. 18A and in a cross sectional view of FIG. 18B.
[0174] In this embodiment, it is also possible to form solder balls [0174] 127 on the backside of the divided segments 133 as the lead pad portions 105 as shown in FIGS. 18A and 18B. In this way, it is possible to mount the semiconductor device 1 b on a mounting substrate by using the solder balls 127, in a manner similar to the semiconductor device shown in FIG. 3B.
[0175] Here, as the second embodiment, an example is shown in which a semiconductor device is fabricated by mounting a semiconductor element [0175] 107 b that is previously separated into a chip on the metal plate 101. However, it is also possible to fabricate semiconductor devices by using a semiconductor wafer which includes semiconductor elements but which is not yet separated into individual chips. This method is now explained as a third embodiment. FIGS. 19A and 19B and FIGS. 20A-20D are perspective views and cross sectional views, respectively, illustrating a method of manufacturing a semiconductor device according to the third embodiment in order of manufacturing steps. First, as shown schematically in the perspective view of FIG. 19A, a plurality of semiconductor elements 203 disposed in a lattice like arrangement are formed on a semiconductor wafer having a disk shape, for example, a silicon wafer 201. Then, bumps 205 are formed in the periphery of each of the semiconductor elements 203 in a manner similar to that of the above-mentioned second embodiment. Since the semiconductor elements 203 can be fabricated on the silicon wafer 201 by using a conventional technology, an explanation thereof is omitted here. On the other hand, as shown schematically in the perspective view of FIG. 19B, a square metal plate 101 a is prepared which has a side length approximately equal to a diameter of the silicon wafer 201. As in the first embodiment, concave trenches 131 a are formed on whole surface of the metal plate 101 a in lattice shape by half-dicing, thereby divided segments 133 c are formed. In this case, a pitch of disposition of the divided segments 133 c is set equal to a pitch of the bumps 205 along the periphery of the semiconductor element 203, or to a pitch of the lattice arrangement of the bumps 205.
[0176] As shown in a cross sectional view of FIG. 20A, the surface of the silicon wafer [0176] 201 is opposed to the metal plate 101 a and the silicon wafer 201 is pressed onto the metal plate 101 a while heating the silicon wafer 201 and the metal plate 101 a. Thereby, the bumps 205 of the silicon wafer 201 are face-down bonded onto the corresponding divided segments 133 c of the metal plate 101 a. Then, as shown in a cross sectional view of FIG. 20B, resin 135 is injected into a space between the silicon wafer 201 and the metal plate 101 a, that is, in each of the concave trenches 131 a of the metal plate 101 a and between the stud bumps 205 of the silicon wafer 201, and the space is sealed with the resin 135. As shown in the cross sectional view of FIG. 20C, the backside of the metal plate 101 a is then polished until the bottom portions of the divided segments 133 a are exposed, that is, until the resin 135 filling the concave trenches 131 a is exposed. By this polishing, the individual divided segments 133 c are separated from each other. However, the divided segments 133 c are kept unified by the resin 135 filling the concave trenches 131 a but electrically isolated with each other. The divided segments 133 c to which the bumps 205 are bonded function as lead pad portions 105 a, that is, mounting electrodes. In FIG. 20C, die pad portions are not shown, but the semiconductor device has the die pad portions. Thereafter, as shown in the cross sectional view of FIG. 20D, the silicon wafer 201 and the metal plate 101 a are cut along dicing lines, that is, scribe lines, of the semiconductor element 203 by full-cut dicing. Thereby, the silicon wafer 201 is divided into separate semiconductor elements 203, and the metal plate 101 a is also divided at the portions of the resin 135. Thus, a plurality of semiconductor devices 2 are fabricated. Also, before or after the dividing process, solder balls 137 are formed on the surface of the lead pad portions 105 a.
[0177] The structure of the semiconductor device [0177] 2 according to the third embodiment resembles the structure of the semiconductor device according to the above-mentioned second embodiment. However, in the semiconductor device 2 according to the third embodiment, both the semiconductor element 203 and the group of the lead pad portions 105 a have the same external size. Also, in the semiconductor device 2, a package resin which coats and seals the semiconductor element 203 does not exist and does not cover the semiconductor element 203. Therefore, it is possible to make the semiconductor devices more compact and thinner. In the semiconductor device according to the third embodiment, although the resin 135 filling the space between the silicon wafer 201 and metal plate 101 a is used, the package resin is not required. Therefore, it is possible to reduce the quantity of resin required for manufacturing the semiconductor devices, and cost of the semiconductor devices can be reduced. Further, in the manufacturing process of the semiconductor device according to the third embodiment, it is possible to perform a dicing process for dividing the silicon wafer 201 into a plurality of semiconductor elements 203 and a dicing process for cutting the resin 135 in the metal plate 101 a at the same time. Also, it is possible to omit a process of individually mounting a plurality of semiconductor element chips onto the respective metal plates. Therefore, it is possible to simplify the whole manufacturing process.
[0178] With reference to the drawings, an explanation will now be made on a first variation of the third embodiment. In this variation, divided segments constituting lead pad portions and die pad portions are formed such that the cross section of each of the divided segments has a crank shape. Thereby, it is possible to mitigate thermal stress caused between a semiconductor device and a mounting substrate when the semiconductor device is mounted on the mounting substrate. Thus, a reliability of a semiconductor device in a condition it is mounted can be improved. A silicon wafer used in this variation is worked similarly to the silicon wafer [0178] 201 used in the above-mentioned third embodiment. However, a metal plate 101 b used in this variation differs from the metal plate 101 a used in the third embodiment. FIG. 21 is a partial enlarged perspective view of the metal plate 101 b used in this variation. As shown in FIG. 21, the metal plate 101 b is a square shaped metal board which has concave trenches 131 b and concave trenches 131 c formed on the face surface and on the backside surface thereof respectively. The concave trenches 131 b on the face side surface each have a depth approximately 40-50 percent of the thickness of the metal plate 101 b and are formed in X and Y directions in a lattice shape. The concave trenches 131 c on the backside surface each have a depth approximately 40-50 percent of the thickness of the metal plate 101 b and are formed in X and Y directions in a lattice shape. FIG. 22 is a schematic plan view showing a relationship between the concave trenches 131 b and the concave trenches 131 c in the metal plate 101 b. In FIG. 22, for the sake of easy understanding, widths of the concave trenches 131 b and 131 c are neglected. The concave trenches 131 b on the face surface side (shown by solid lines in FIG. 22) and the concave trenches 131 c on the back side (shown by dotted lines in FIG. 22) have the same width of the trenches and the same pitch of the trenches. However, the concave trenches 131 c are shifted from the concave trenches 131 b both in the X and Y directions by distances corresponding to the width of the trenches.
[0179] FIG. 23A through FIG. 23E are cross sectional views showing a method of manufacturing a semiconductor device by using the above-mentioned metal plate [0179] 101 b according to the first variation of the third embodiment in order of process steps. As shown in FIG. 23A, the bumps 205 of the silicon wafer 201 are bonded to the divided segments 133 d on the face side surface of the metal plate 101 b as in the above-mentioned third embodiment. Then, as shown in FIG. 23B, resin 135 a is injected into a space between the silicon wafer 201 and the metal plate 101 b. As shown in FIG. 23C, a photoresist mask 139 is formed on the back side surface of the metal plate 101 b. The photoresist mask 139 covers areas which are to be left as lead pad portions and die pad portions in the metal plate 101 b. FIG. 24 is a schematic plan view illustrating the areas in which the photoresist mask 139 is to be formed. For the sake of easy understanding, schematic locations of the concave trenches 131 b are also shown in FIG. 24, although the width of each of the concave trenches 131 b is neglected. As shown in FIG. 24, the photoresist mask 139 is formed as minute rectangular pattern portions which are disposed regularly in the X and Y directions and which have the same pitches as those of the concave trenches 131 b or the concave trenches 131 c. When the concave trenches 131 b and the concave trenches 131 c are perspectively viewed from the back surface side of the metal plate 101 b, each of the minute patterns of the photoresist mask 139 is disposed such that both a part of a concave trench 131 b and a part of a concave trench 131 c are covered by the minute pattern. Since a portion of each minute patterns of the photoresist mask 139 is buried into a concave trench 131 b, each minute pattern of the photoresist mask 139 has a gourd-like solid shape. Then, as shown in FIG. 23D, the metal plate 101 b is etched through the whole thickness by using the photoresist mask 139 as an etching mask. Thereby, divided segments 133 e are formed as independent pieces. Thereafter, the remained photoresist mask 139 is removed. FIG. 25 is a schematic perspective view illustrating a solid shape of each of the divided segments 133 e. As can be seen from FIG. 25, a cross section of each of the divided segments 133 e in the direction of the thickness becomes a crank shape. Among the divided segments 133 e, the divided segments 133 e bonded to the bump 205 of the silicon wafer 201 are formed as lead pad portions 105 b. The lead pad portions 105 b are unified and joined with the silicon wafer 201 due to the bonding by the bumps 205 and due to the bonding by the resin 135 a.
[0180] Thereafter, as shown in FIG. 23E, the silicon wafer [0180] 201 and the metal plate 101 b are cut at predetermined locations by a dicing saw and divided into pieces each having a predetermined size. Thereby, individual semiconductor devices 2 a are formed. In this case, the metal plate 101 b is already divided by the process steps described with reference to FIG. 23D. Thus, in practice, it is only necessary to cut the silicon wafer 201 and the resin 135 in the cutting process illustrated in FIG. 23E. In the semiconductor device 2 a, each of the lead pad portions 105 b has a shape which is bent into a crank-like shape. When the semiconductor device 2 a is mounted on a mounting substrate as shown, for example, in FIGS. 3A and 3B, there is a possibility that stress is applied on the lead pad portions 105 b due to the difference of thermal expansion coefficients between the mounting substrate and the semiconductor element of the semiconductor device. However, even in such case, it is possible to absorb such stress at the crank-like bent portion of each lead pad portions 105 b. Thereby, it is possible to avoid breakage of coupling between the lead pad portions 105 b and the mounting substrate. Therefore, reliability of mounting of the semiconductor device can be improved. Although not shown in the drawing, it is possible to fill the spaces between the divided segments 133 e with resin and to flatten the backside of the semiconductor device, and, thereafter, to form a solder ball on the backside surface of each of the lead pad portions 105 b. Alternatively, in place of the solder ball, it is possible to form a solder plated portion and the like on the backside surface of each of the lead pad portions 105 b. Even in such case, it is possible to retain the above-mentioned function of mitigating the stress by the lead pad portions 105 b.
[0181] An explanation will now be made on a second variation of the third embodiment. In the above-mentioned first variation, the semiconductor device [0181] 2 a is fabricated by forming the photoresist mask on the backside surface of the metal plate 101 b and by selectively etching the metal plate 101 b. However, if the width of each of the concave trenches formed in lattice shape is enlarged, it is possible to omit the process of selectively removing the metal plate by etching. Such method is explained as the second variation. FIG. 26A and FIG. 26B are cross sectional views showing a method of manufacturing a semiconductor device as the second variation of the third embodiment in order of manufacturing steps. In the second variation, the semiconductor device is formed from a disk shaped semiconductor wafer, here, a silicon wafer 201, as shown in FIG. 19A. As mentioned above, on the silicon wafer 201, there are formed semiconductor elements 203 disposed in a lattice arrangement. Also, as in the third embodiment, bumps 205 are formed in the peripheral portion of each of the semiconductor elements 203. On the other hand, a metal plate 101 c is prepared which is a square shaped metal board and which has the side length approximately equal to the diameter of the silicon wafer 201. Then, concave trenches 131 d are formed on the face side surface thereof, and thereby divided segments 133 f are formed. The concave trenches 131 c each have a depth approximately 50 percent of the thickness of the metal plate 101 c and are formed in X and Y directions in a lattice shape. In this case, a pitch of disposition of the divided segments 133 f is set equal to a pitch of the bumps 205 along the periphery of the semiconductor element 203, or to a pitch of the lattice arrangement of the bumps 205.
[0182] As shown in a cross sectional view of FIG. 26A, the backside surface of the silicon wafer [0182] 201 is opposed to the metal plate 101 c and the silicon wafer 201 is pressed onto the metal plate 101 c while heating the silicon wafer 201 and the metal plate 10 c. Thereby, the bumps 205 of the silicon wafer 201 are face-down bonded onto the corresponding divided segments 133 f of the metal plate 10 c. Then, as shown in a cross sectional view of FIG. 26B, resin 135 b is injected into a space between the silicon wafer 201 and the metal plate 10 c, that is, in each of the concave trenches 131 d of the metal plate 101 c and between the bumps 205 of the silicon wafer 201, and the space is sealed by the resin 135 b. Thereafter, concave trenches 131 e are formed on the backside surface of the metal plate 10 c. Each of the concave trenches 131 d has a depth approximately 50 percent of the thickness of the metal plate 101 c and are formed in X and Y directions in a lattice shape. As in the first variation, the concave trenches 131 d on the face surface side and the concave trenches 131 e on the back side have the same width of the trenches and the same pitch of the trenches. However, the concave trenches 131 e are shifted from the concave trenches 131 d both in the X and Y directions by distances smaller than the width of the trenches 131 d or 131 e. That is, the concave trenches 131 d and the concave trenches 131 e partially overlap with each other. In this way, by forming the concave trenches 131 e from the backside of the metal plate 101 c, it is possible to form individually divided segments 133 g. Each of the divided segments 133 g has a crank-like cross section in the direction of the thickness thereof. Thereafter, although not shown in the drawing, the silicon wafer 201 and the metal plate 101 c are cut at predetermined locations by a dicing saw and divided into pieces each having a predetermined size. Thereby, individual semiconductor devices are formed. In this case, the metal plate 101 c is already divided in the process steps for forming the concave trenches 131 e on the backside described with reference to FIG. 26B. Thus, in practice, it is only necessary to cut the silicon wafer 201 and the resin 135 b in the cutting process.
[0183] With reference to FIGS. 27A and 27B, FIGS. 28A and 28B, and FIGS. [0183] 29A-29D, an explanation will be made on a fourth embodiment of the present invention. In this embodiment, a metal plate is at first full-cut diced to form separate divided segments, and the divided segments are used to constitute die pad portions and lead pad portions. As shown in a top plan view of FIGS. 27A and in a cross sectional view of FIG. 27B, an adhesive sheet 141 is stuck on the backside surface of a metal plate 101 d having a predetermined size. The adhesive sheet 141 holds divided segments 133 h which are divided in a later process. Also, the adhesive sheet 141 has a thickness and a stiffness sufficient to maintain flatness of the sheet. Then, as shown in a top plan view of FIGS. 28A and in a cross sectional view of FIG. 28B, the metal plate 101 d is full-cut diced from the face side surface, and concave trenches 131 f extending in X and Y directions are formed in the metal plate 101 d. Thereby, the divided segments 133 h are formed which are disposed in a lattice shape. Although these divided segments 133 h are completely separated, a condition of initial arrangement of the divided segments 133 h is maintained by the adhesive sheet 141.
[0184] Thereafter, process steps approximately similar to those shown in FIGS. 6A and 6B through FIGS. 9A and 9B of the first embodiment are performed. That is, as shown in a cross sectional view of FIG. 29A, a semiconductor element [0184] 107 is mounted on the surface of the metal plate 101 d by using a mounting material 109 a. Then, as shown in a cross sectional view of FIG. 29B, electrodes of the semiconductor element 107 and the divided segments 133 h which become lead pad portions 105 c located in the periphery of the semiconductor element 107 are electrically coupled by bonding wires 111. As shown in the cross sectional view of FIG. 29C, resin is then molded or applied on the surface of the metal plate 101 d. Thereby, a package resin portion 113 c is formed which molds the semiconductor element 107 and the bonding wires 111. Thereafter, as shown in the cross sectional view of FIG. 29D, the adhesive sheet 141 stuck on the backside surface of the metal plate 101 d is peeled off. Thereby, it is possible to fabricate a semiconductor device according to the fourth embodiment which has a structure similar to that of the first embodiment. Differing from the first through third embodiments, in the fourth embodiment, it is not necessary to perform polishing of the backside surface of the metal plate 101 d. Although not shown in the drawing, when a plurality of semiconductor elements are molded together by a package resin portion, it is possible to obtain separate semiconductor devices by cutting the package resin portion into individual pieces. Also, as shown in FIGS. 2A and 2B, an insulating resist film may be or may not be selectively applied on the backside surface of each of the divided segments 133 h constituting die pad portions 103 c.
[0185] In the above-mentioned fourth embodiment, the adhesive sheet [0185] 141 is used which is not required as a constituent of the semiconductor device. In this point, the fourth embodiment may not be advantageous in reducing the number of components required for fabricating the semiconductor device. An explanation will now be made on a method of manufacturing a semiconductor device as a variation of the fourth embodiment. This method does not use such unnecessary component, but realizes fabrication of a semiconductor device in a manner similar to the fourth embodiment. FIGS. 30A-30F are schematic cross sectional views illustrating a manufacturing method of this variation in order of manufacturing steps. First, as shown in FIG. 30A, a resist sheet 143 is bonded on the backside surface of the metal plate 101 e. The resist sheet 143 is made of material which does not adhere to solder and the like and which has high heat resistance and high moisture resistance. FIG. 31 is a schematic plan view illustrating the resist sheet 143. As shown in FIG. 31, in the resist sheet 143, openings 143 a are formed at portions corresponding to locations in which mounting electrodes of a semiconductor device to be fabricated are disposed. As shown in FIG. 30B, as in the fourth embodiment, a metal plate 101 e is full-cut diced to form concave trenches 131 g extending in X and Y directions and, thereby, separate divided segments 133 j are formed in lattice arrangement. FIG. 32 is a schematic plan view illustrating a positional relationship between the opening portions 143 a and the divided segments 133 j. As shown in FIG. 32, the concave trenches 131 g are formed in a predetermined pitch such that locations of portions of the divided segments 133 j correspond to the locations of the openings 143 a of the resist sheet 143. The divided segments 133 j are hold in a unified condition by the resist sheet 143.
[0186] Thereafter, process steps approximately similar to those of the above-mentioned fourth embodiment are performed. That is, as shown in a cross sectional view of FIG. 30C, two semiconductor elements [0186] 107 are mounted on the surface of the metal plate 101 e by using mounting material portions 109 b. Then, as shown in a cross sectional view of FIG. 30D, electrodes of the semiconductor elements 107 and the divided segments 133 j which become lead pad portions 105 d located in the periphery of the semiconductor elements 107 are electrically coupled by bonding wires 111. As shown in the cross sectional view of FIG. 30E, resin 113 d is then molded or applied on the surface of the metal plate 101 e. Thereby, a package resin portion 113 d is formed which molds the semiconductor elements 107 and the bonding wires 111. Thereafter, the package resin portion 113 d is cut and also the resist sheet 143 is cut to fabricate individual semiconductor devices. Then, as shown in FIG. 30F, solder balls 137 are joined on the backside surface of the divided segments 133 j as the lead pad portions 105 d exposed via the openings 143 a of the resist sheet 143. In this case, since the resist sheet 143 does not have adhesiveness with the solder, there is little possibility that the divided segments 133 j exposing via adjacent openings 143 a are short-circuited by the solder. As a result, the resist sheet 143 functions like the resist film 115 in the first embodiment. In this variation, the resist sheet 143 which supports the divided segments obtained when the metal plate 101 e is full-cut diced can be used as the resist film on the backside of the semiconductor device as it is. Therefore, components can be effectively utilized.
[0187] In the fourth embodiment and the variation thereof, the semiconductor elements are mounted on the metal plate while keeping the surface of the semiconductor elements on which the electrodes are formed upside. Then, the electrodes of the semiconductor elements are electrically coupled with the divided segments by the bonding wires. However, in these structures, it is also possible to form bumps on the surface of each of the semiconductor elements and to mount the semiconductor elements on the metal plate in the face-down manner, as in the second embodiment, such that the bumps are coupled with the divided segments of the metal plate. In such case, it is also possible to mount a silicon wafer on which a plurality of semiconductor elements are formed on a metal plate, and to perform molding by package resin. Thereafter, the silicon wafer is cut to form separate semiconductor devices. [0187]
[0188] In the semiconductor devices according to the above-mentioned embodiments and variations thereof, lead pad portions and die pad portions are formed by using divided segments obtained by dividing a metal plate. However, it is also possible to finally remove a portion of the metal plate in an area corresponding to die pad portions, that is, divided segments, and to form the die pad portions by using mounting material. Such method will now be explained as a fifth embodiment. FIGS. 33A and 33B through FIGS. 36A and 36B are plan views and cross sectional views, illustrating a method of manufacturing a semiconductor device as the fifth embodiment in order of manufacturing steps. First, as in the first embodiment mentioned above with reference to FIGS. 4A and 4B, a plurality of concave trenches [0188] 131 h extending in X and Y directions are formed in a square shaped metal plate 101 f to form divided segments 133 k in lattice arrangement. Thereafter, as shown in the top plan view of FIG. 33A and in the cross sectional view of FIG. 33B, a central area of the metal plate 101 f is caved toward the backside of the metal plate 101 f by press work. Thereby, a concave portion 151 is formed in the central area of the metal plate 101 f. In this case, the level of the inner bottom portion of the concave portion 151 becomes lower than the level of the backside surface of the metal plate 101 f, that is, the divided segments 133 k, at the peripheral portion of the metal plate 101 f which is not caved.
[0189] As shown in the top plan view of FIG. 34A and in the cross sectional view of FIG. 34B, a semiconductor element [0189] 107 is mounted on the concave portion 151 in the central area of the metal plate 101 f by using mounting material 109 c. In this case, by adjusting a quantity of the mounting material 109 c, the level of the backside surface of the mounted semiconductor element 107 becomes higher than the level of the bottom portion of each of the concave trenches 131 h in the peripheral area external to the concave portion 151. Also, the mounting material 109 c are made of material such as silver paste and the like which has high moisture resistance and high heat resistance and which has some mechanical strength. Thereafter, electrodes 108 of the semiconductor element 107 and the face side surfaces of the divided segments 133 k disposed in the periphery of the semiconductor element 107 are electrically coupled via-bonding wires 111. Then, as shown in the partially cutaway top plan view of FIG. 35A and in the cross sectional view of FIG. 35B, resin is molded or applied on the face surface of the metal plate 101 f. Thereby, the package resin portion 113 e is formed which molds the semiconductor element 107 and the bonding wires 111. In this case, a portion of the package resin portion 113 e enters into the concave trenches 131 h in the peripheral area external to the concave portion 151 and, thereby, the divided segments 133 k are joined together.
[0190] As shown in the bottom plan view of FIG. 36A and in the cross sectional view of FIG. 36B, the metal plate [0190] 101 f is polished flat from the backside thereof until reaching the bottom portions of the concave trenches 131 h. By this polishing, the central portion of the metal plate 101 f constituting the concave portion 151 is removed. Thereby, the mounting material 109 c which is used for mounting the semiconductor element 107 on the metal plate 101 f is exposed. Thus, the semiconductor element 107 is mounted on and supported by the mounting material portion 109 c. Also, if necessary, the package resin portion 113 e is cut at predetermined locations by using a dicing saw. The divided segments 133 k remain only at the peripheral portion of the mounting material 109 c and form the lead pad portions 105 e. In the fifth embodiment, by controlling the amount of polishing at the backside of the divided segments 133 k constituting the lead pad portions 105 e and by reducing the height of the divided segments 133 k, it is possible to fabricate very thin semiconductor devices. Also, the fifth embodiment differs from the first through fourth embodiments in that the die pad portion is replaced from the divided segments of the metal plate to the mounting material 109 c.
[0191] In the above-mentioned semiconductor devices according to the first through fifth embodiments and the variations thereof, semiconductor integrated circuit chips are used as semiconductor elements. However, it is possible to apply the present invention to discrete devices such as diodes, transistors and the like. As a sixth embodiment, an explanation will be made on an example in which the present invention is applied to diodes. FIGS. 37A and 37B are a top plan view and a cross sectional view, respectively, illustrating a schematic structure of a diode as the sixth embodiment. In FIG. 37A, for the sake of easy understanding, a package resin portion [0191] 113 f is removed except a portion between divided segments 133 m. As shown in FIG. 37A and 37B, one of the divided segments 133 m is used as a die pad portion 103 f (or a lead pad portion on the cathode side), and a diode chip 107 c is mounted on the die pad portion 103 f via mounting material 109 d. The other divided segment 133 m adjacent the die pad portion 103 f is used as a lead pad portion 105 f on the anode side, and the diode chip 107 c and the lead pad portion 105 f on the anode side are electrically connected via a bonding wire 111 a. These divided segments 133 m, the diode chip 107 c and the like are molded by the package resin 113 f. In this way, a discrete diode device 3 is fabricated. As shown in a plan view of FIG. 38A and in a cross sectional view of FIG. 38B, it is possible to apply the present invention to a semiconductor device in which a plurality of diode chips are mounted, that is, to a diode array. In the diode array 3 a of FIGS. 38A and 38B, a plurality of divided segments 133 m are used as die pad portions 103 f, and a diode chip 107 c is mounted on each of the die pad portions 103 f via mounting material portions 109 d. The other divided segments 133 m adjacent the die pad portions 103 f are used as lead pad portions 105 f on the anode side, and the diode chips 107 c and the lead pad portions 105 f on the anode side are electrically connected via bonding wires 111 a. These divided segments 133 m, the diode chips 107 c and the like are molded and unified by the package resin 113 f. In this way, the semiconductor device 3 a in which a plurality of diode chips are mounted, that is, the diode array 3 a is fabricated. Although not shown in the drawings, it is possible to apply the present invention to a discrete transistor in which a transistor is mounted, or to a transistor array in which a plurality of transistors are mounted. In such case, for example, one divided segment on which a transistor chip is mounted is used as a die pad portion which is also used as a lead pad portion on the collector side. Other two divided segments are used as lead pad portions for a base and an emitter. In case the transistor is a field effect transistor, respective divided segments are used as lead pad portions for a gate, a source and a drain.
[0192] FIG. 39A through FIG. 39D are cross sectional views illustrating a method of manufacturing a discrete diode to which the present invention is applied according to the above-mentioned sixth embodiment. First, as the first embodiment illustrated in FIGS. 4A and 4B, a plurality of concave trenches [0192] 131 j are formed on the surface of a metal plate 101 g in X and Y directions, to form divided segments 133 m in a lattice like arrangement. Then, as shown in FIG. 39A, among the divided segments 133 m, diode chips 107 c are mounted on every other divided segments 133 m via mounting material 109 d. A substrate portion of each diode chip 107 c is composed of an N-type semiconductor, and functions as a cathode of a diode. Thus, the cathode of each diode chip 107 is electrically coupled with the divided segment 133 m. Then, an anode electrode provided on the face surface of each of the diode chips 107 c not shown in the drawing is electrically coupled via the bonding wire 111 a with the divided segment 133 m disposed adjacent to the divided segment 133 m on which the diode chip 107 c is mounted. On the surface of the metal plate 101 g, resin is then molded or applied. That is, the diode chips 107 c and the bonding wires 111 a are molded by a package resin portion 113 f. In this case, portions of the package resin 113 f enter into the concave trenches 131 j.
[0193] As shown in FIG. 39C, the metal plate [0193] 101 f is polished or etched flat from the backside thereof until reaching the bottom portions of the concave trenches 131 j. By this polishing, the divided segments 133 m are divided into individual pieces. In this case, the divided segments 133 m are unified by the package resin portion 113 f but are electrically isolated from each other. Then, as shown in FIG. 39D, the package resin portion 113 f is cut into separate pieces by using a dicing saw not shown in the drawing. In this case, the package resin portion 113 f can be cut into pieces each having a pair of the divided segments 133 m which include the divided segment 133 m as the die pad portion 103 f and the divided segment 133 m as the lead pad portion 105 f. By appropriately selecting cutting portions, it is possible to fabricate individual diodes 3 each including one diode chip as shown in FIGS. 37A and 37B, or to fabricate diode arrays 3 a each including a plurality of diode chips as shown in FIGS. 38A and 38B.
[0194] In the sixth embodiment, it is possible to use a single standardized metal plate [0194] 101 f even when discrete diodes, or various diode arrays including various number of diode chips are to be fabricated. The diode chips are mounted on such metal plate and molded by package resin. By only changing the portions to be cut finally, it is possible to form discrete diodes, or various diode arrays including various number of diode chips. Therefore, it is not necessary to prepare a plurality kinds of lead members to fabricate a plurality kinds of diode arrays. Also, it is not necessary to prepare a plurality kinds of molding die for package resin. Therefore, it is possible to simplify a manufacturing process, and to reduce costs of semiconductor devices.
[0195] The above-mentioned first through sixth embodiments and the variations thereof show typical embodiments or examples of the present invention. By appropriately combining these embodiments and the like, it is possible to provide further diversified semiconductor devices and method of manufacturing the same. Also, with respect to a technique in each of the process steps described in the embodiments and variations thereof, it is possible to replace it by any of various conventionally proposed techniques while retaining advantageous effects mentioned above. [0195]
[0196] As mentioned above, in a semiconductor device according to the present invention, a plurality of divided segments are formed from a conductor plate or board, and lead pad portions are constituted of the divided segments which are electrically coupled with electrodes of a semiconductor element. Therefore, by appropriately determining which divided segments are used as lead pad portions depending on the size and kind of each of the semiconductor elements, it is possible to commonly utilize the divided segments for the semiconductor elements having different sizes and kinds to form device packages. Also, it is possible to form die pad portions by using portions of the divided segments and to mount a semiconductor element on the die pad portions. In this case, other portions of the divided segments are used as lead pad portions and electrodes of the semiconductor element are electrically coupled with the lead pad portions via the bonding wires. Alternatively, it is possible to electrically couple bumps provided on electrodes of a semiconductor element with divided segments to form lead pad portions. Thereby, it is possible to mount or dispose a semiconductor element in face-up condition or in face-down condition. The lead pad portions may be disposed in the periphery of the package, or may be disposed in the bottom portion of the package in lattice-like arrangement. The same standard conducting plate can be utilized to fabricate surface-mount type semiconductor devices having lead-less structure, even if the semiconductor devices have different sizes and/or kinds. [0196]
[0197] In the method of manufacturing a semiconductor device according to the present invention, divided segments are defined by forming concave trenches in a conductor plate. A semiconductor element is mounted on the divided segments, and the semiconductor element and the divided segments are electrically coupled. Thereafter, the backside portion of the conductor plate is removed to form individual divided segments. Therefore, it is possible to easily perform a process of mounting a semiconductor element, a process of electrical connection between the semiconductor element and the divided segments, and a process of forming a package resin portion. Also, it is possible to fabricate a semiconductor device which has a plurality of lead pad portions finally insulated from each other. Therefore, according to the present invention, the number of parts and the number of process steps do not increase uselessly, and manufacturing process can be simplified. [0197]
[0198] In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative sense rather than a restrictive sense, and all such modifications are to be included within the scope of the present invention. Therefore, it is intended that this invention encompasses all of the variations and modifications as fall within the scope of the appended claims. [0198]

权利要求:
Claims (50)
[1" id="US-20010009301-A1-CLM-00001] 1. A semiconductor device comprising:
a semiconductor element;
a plurality of segments formed by dividing a conductive plate, at least one of said segments being electrically coupled with an electrode of said semiconductor element; and
a resin material portion supporting said plurality of segments and said semiconductor element together.
[2" id="US-20010009301-A1-CLM-00002] 2. A semiconductor device as set forth in
claim 1 , wherein said at least one of said segments electrically coupled with said electrodes of said semiconductor element constitute lead pad portions as mounting electrodes, and at least one of other segments among said plurality of segments constitute die pad portions on which said semiconductor element is mounted.
[3" id="US-20010009301-A1-CLM-00003] 3. A semiconductor device as set forth in
claim 2 , wherein, among said plurality of segments, at least one of said segments located under said semiconductor element constitute die pad portions, and at least one of said segments which are disposed in the peripheral portion of said segments constituting said die pad portions and which are electrically coupled with said electrodes of said semiconductor element via bonding wires constitute lead pad portions.
[4" id="US-20010009301-A1-CLM-00004] 4. A semiconductor device as set forth in
claim 3 , wherein said resin material portion seals said semiconductor element and said bonding wires, and fills the space between said segments as said lead pad portions among said plurality of segments.
[5" id="US-20010009301-A1-CLM-00005] 5. A semiconductor device as set forth in
claim 2 , wherein said semiconductor element is mounted on said at least one of said segments as die pad portions via mounting material or tape-like adhesive.
[6" id="US-20010009301-A1-CLM-00006] 6. A semiconductor device as set forth in
claim 2 , wherein a part of said segments located under said semiconductor element constitute die pad portions, and other part of said segments located under said semiconductor element are electrically coupled with electrodes of said semiconductor element via bumps and constitute lead pad portions.
[7" id="US-20010009301-A1-CLM-00007] 7. A semiconductor device as set forth in
claim 6 , wherein said resin material portion seals said semiconductor element, and fills the space between said semiconductor element and said segments located under said semiconductor element and the space between said segments located under said semiconductor element.
[8" id="US-20010009301-A1-CLM-00008] 8. A semiconductor device as set forth in
claim 1 , wherein said plurality of segments are formed by dividing a conductive plate into a lattice-like arrangement.
[9" id="US-20010009301-A1-CLM-00009] 9. A semiconductor device as set forth in
claim 1 , wherein each of said segments has a crank-like cross section in the direction of thickness of said conductive plate.
[10" id="US-20010009301-A1-CLM-00010] 10. A semiconductor device as set forth in
claim 1 , wherein said plurality of segments are disposed around said semiconductor element but are not disposed under said semiconductor element, at least one of said segments are electrically coupled with electrodes of said semiconductor element via bonding wires and constitute lead pad portions as mounting electrodes, and said resin material portion seals said semiconductor element and said bonding wires and fills the space between respective segments of said plurality of segments.
[11" id="US-20010009301-A1-CLM-00011] 11. A semiconductor device as set forth in
claim 2 , wherein said semiconductor element is a semiconductor integrated circuit chip, and electrodes of said semiconductor integrated circuit chip are respectively coupled with said segments as lead pad portions among said plurality of segments.
[12" id="US-20010009301-A1-CLM-00012] 12. A semiconductor device as set forth in
claim 2 , wherein said semiconductor element is a diode chip, said diode chip is mounted on one of said plurality of segments, and an electrode of said diode chip is electrically coupled with other one of said segments adjacent said divided segment on which said diode chip is mounted.
[13" id="US-20010009301-A1-CLM-00013] 13. A semiconductor device as set forth in
claim 2 , wherein said semiconductor element is a transistor chip, said transistor chip is mounted on one of said plurality of segments, and electrodes of said transistor chip are electrically coupled with two of said segments adjacent said divided segment on which said transistor chip is mounted.
[14" id="US-20010009301-A1-CLM-00014] 14. A semiconductor device as set forth in
claim 2 , wherein a ball-like electrode is formed on the backside surface of said at least one of said segments constituting said lead pad portions.
[15" id="US-20010009301-A1-CLM-00015] 15. A semiconductor device as set forth in
claim 6 , wherein said bumps are solder bumps or studbumps.
[16" id="US-20010009301-A1-CLM-00016] 16. A semiconductor device as set forth in
claim 2 , wherein a resist film is formed on the backside surface of said at least one of said segments constituting said die pad portions.
[17" id="US-20010009301-A1-CLM-00017] 17. A semiconductor device as set forth in
claim 2 , wherein an outer dimension of a group of said segments which constitute said die pad portions and said lead pad portions is larger than an outer dimension of said semiconductor element.
[18" id="US-20010009301-A1-CLM-00018] 18. A semiconductor device as set forth in
claim 6 , wherein an outer dimension of a group of said segments which constitute said die pad portions and said lead pad portions is substantially equal to an outer dimension of said semiconductor element.
[19" id="US-20010009301-A1-CLM-00019] 19. A method of manufacturing a semiconductor device comprising:
preparing a conductive plate;
forming concave-trenches in said conductive plate to form a plurality of segments;
preparing a semiconductor element;
mounting a semiconductor element on said conductive plate having said concave trenches formed therein;
disposing resin material on said conductive plate wherein a part of said resin material enters at least a part of said concave trenches; and
removing the backside portion of said conductive plate so as to expose bottom portions of said concave trenches.
[20" id="US-20010009301-A1-CLM-00020] 20. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein, in said removing the backside of said conductive plate, the backside of said conductive plate is polished or etched so as to expose bottom portions of said concave trenches.
[21" id="US-20010009301-A1-CLM-00021] 21. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein, in said mounting a semiconductor element on said conductive plate, said semiconductor element is mounted on at least one of said segments;
wherein said method further comprises electrically coupling electrodes of said semiconductor element with segments disposed around said at least one of said segments on which said semiconductor element is mounted; and
wherein, in said disposing said resin material on said conductive plate, said semiconductor element and said bonding wires are sealed by said resin material, and said resin material fills said concave trenches between segments disposed around said at least one of said segments on which said semiconductor element is mounted.
[22" id="US-20010009301-A1-CLM-00022] 22. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein, in said preparing a semiconductor element, a semiconductor element having bumps formed thereon is prepared;
wherein, in said mounting said semiconductor element on said conductive plate, electrodes of said semiconductor element are electrically coupled with at least one of segments disposed under said semiconductor element via said bumps; and
wherein, in said disposing said resin material on said conductive plate, said semiconductor element is sealed by said resin material, and said resin material fills a space between said semiconductor element and said conductive plate.
[23" id="US-20010009301-A1-CLM-00023] 23. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein, in said forming concave trenches in said conductive plate to form a plurality of segments, said concave trenches are formed in lattice-like arrangement.
[24" id="US-20010009301-A1-CLM-00024] 24. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein, in said forming concave trenches in said conductive plate to form a plurality of segments, said concave trenches are formed by using a technology selected from a group consisting of half-cut dicing, half-etching and press working.
[25" id="US-20010009301-A1-CLM-00025] 25. A method of manufacturing a semiconductor device as set forth in
claim 21 , wherein, in said mounting a semiconductor element on said conductive plate, said semiconductor element is mounted on said conductive plate via mounting material or tape-like adhesive.
[26" id="US-20010009301-A1-CLM-00026] 26. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein said method further comprises caving a portion of said conductive plate to form a concave portion, before said mounting a semiconductor element on said conductive plate;
wherein, in said mounting a semiconductor element on said conductive plate, said semiconductor element is mounted in said concave portion via mounting material;
wherein said method further comprises electrically coupling electrodes of said semiconductor element with segments disposed around said concave portion via bonding wires;
wherein, in said disposing said resin material on said conductive plate, said semiconductor element and said bonding wires are sealed by said resin material, and said resin material fills said concave trenches between segments disposed around said concave portion; and
wherein, in said removing the backside portion of said conductive plate, said mounting material is exposed.
[27" id="US-20010009301-A1-CLM-00027] 27. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein said semiconductor element is a semiconductor integrated circuit chip
[28" id="US-20010009301-A1-CLM-00028] 28. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein said semiconductor element is a diode chip;
wherein, in said mounting said semiconductor element on said conductive plate, said diode chip is mounted on one of said plurality of segments;
wherein said method further comprises electrically coupling an electrode of said diode chip with one of said segments adjacent said divided segment on which said diode chip is mounted via a bonding wire; and
wherein, in said disposing said resin material on said conductive plate, said diode chip and said bonding wire are sealed by said resin material, and said resin material fills the concave trench between said divided segment electrically coupled with said electrode of said diode chip and said divided segment on which said diode chip is mounted.
[29" id="US-20010009301-A1-CLM-00029] 29. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein said semiconductor element is a transistor chip;
wherein, in said mounting said semiconductor element on said conductive plate, said transistor chip is mounted on one of said plurality of segments;
wherein said method further comprises electrically coupling electrodes of said transistor chip with two of said segments adjacent said divided segment on which said transistor chip is mounted via bonding wires; and
wherein, in said disposing said resin material on said conductive plate, said transistor chip and said bonding wires are sealed by said resin material, and said resin material fills the concave trenches between said segments electrically coupled with said electrodes of said transistor chip and said divided segment on which said transistor chip is mounted.
[30" id="US-20010009301-A1-CLM-00030] 30. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein, in said disposing said resin material on said conductive plate, said resin material is disposed by using a technology selected from a group consisting of molding by a metal die, coating, and potting.
[31" id="US-20010009301-A1-CLM-00031] 31. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein, in said preparing a semiconductor element, a plurality of semiconductor elements are prepared;
wherein, in said mounting said semiconductor element on said conductive plate, said plurality of semiconductor elements are mounted on said conductive plate; and
wherein, in said disposing said resin material on said conductive plate, said plurality of semiconductor elements are sealed by said resin material.
[32" id="US-20010009301-A1-CLM-00032] 32. A method of manufacturing a semiconductor device as set forth in
claim 31 , wherein said method further comprises, after removing the backside portion of said conductive plate, cutting said resin material in predetermined locations to form separate semiconductor devices each including at least one semiconductor element.
[33" id="US-20010009301-A1-CLM-00033] 33. A method of manufacturing a semiconductor device as set forth in
claim 19 , wherein, in said forming concave trenches in said conductive plate to form a plurality of segments, said concave trenches are formed in lattice-like arrangement;
wherein, in said preparing a semiconductor element, a semiconductor wafer on which a plurality of semiconductor elements are formed is prepared;
wherein, in said mounting said semiconductor element on said conductive plate, said semiconductor wafer is mounted on said conductive plate and electrodes of each semiconductor element formed in said semiconductor wafer are electrically coupled with corresponding segments of said plurality of segments via bumps;
wherein, in said disposing said resin material on said conductive plate, said resin material fills a space between said semiconductor wafer and said conductive plate; and
wherein said method further comprises, after removing the backside portion of said conductive plate, cutting said semiconductor wafer and said resin material in predetermined locations to form separate semiconductor devices each including at least one semiconductor element.
[34" id="US-20010009301-A1-CLM-00034] 34. A method of manufacturing a semiconductor device comprising:
preparing a conductive plate;
preparing a supporting sheet;
sticking said conductive plate on said supporting sheet;
cutting said conductive plate stuck on said supporting sheet to form a plurality of segments supported by said supporting sheet;
preparing a semiconductor element;
mounting a semiconductor element on at least one of said plurality of segments; and
disposing resin material on said plurality of segments, wherein a part of said resin material enters at least a part of spaces between said segments.
[35" id="US-20010009301-A1-CLM-00035] 35. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein said method further comprises peeling said supporting sheet, after disposing said resin material.
[36" id="US-20010009301-A1-CLM-00036] 36. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein said supporting sheet has opening portions at predetermined locations, and is made of material which does not adhere to solder; and
wherein, in said cutting said conductive plate stuck on said supporting sheet to form a plurality of segments supported by said supporting sheet, at least one of said segments is exposed via said opening portions of said supporting sheet.
[37" id="US-20010009301-A1-CLM-00037] 37. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein said method further comprises electrically coupling electrodes of said semiconductor element with segments disposed around said at least one of said segments on which said semiconductor element is mounted via bonding wires; and
wherein, in said disposing said resin material, said semiconductor element and said bonding wires are sealed by said resin material, and said resin material fills spaces between segments disposed around said at least one of said segments on which said semiconductor element is mounted.
[38" id="US-20010009301-A1-CLM-00038] 38. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein, in said preparing a semiconductor element, a semiconductor element having electrodes on which bumps are formed is prepared;
wherein, in said mounting a semiconductor element on at least one of said plurality of segments, electrodes of said semiconductor element are electrically coupled with at least one of said segments located under said semiconductor element via said bumps; and
wherein, in said disposing said resin material, said semiconductor element is sealed by said resin material, and said resin material fills spaces between segments disposed under said semiconductor element and spaces between said semiconductor element and said segments located under said semiconductor element.
[39" id="US-20010009301-A1-CLM-00039] 39. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein, in said cutting said conductive plate stuck on said supporting sheet to form a plurality of segments supported by said supporting sheet, said conductive plate is cut into lattice-like arrangement, and said supporting sheet is not cut substantially.
[40" id="US-20010009301-A1-CLM-00040] 40. A method of manufacturing a semiconductor device as set forth in
claim 37 , wherein, in said mounting a semiconductor element on at least one of said segments, said semiconductor element is mounted on said at least one of said segments via mounting material or tape-like adhesive.
[41" id="US-20010009301-A1-CLM-00041] 41. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein said semiconductor element is a semiconductor integrated circuit chip
[42" id="US-20010009301-A1-CLM-00042] 42. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein said semiconductor element is a diode chip;
wherein, in said mounting said semiconductor element on at least one of said segments, said diode chip is mounted on one of said plurality of segments;
wherein said method further comprises electrically coupling an electrode of said diode chip with one of said segments adjacent said divided segment on which said diode chip is mounted via a bonding wire; and
wherein, in said disposing said resin material, said diode chip and said bonding wire are sealed by said resin material, and said resin material fills a space between said divided segment electrically coupled with said electrode of said diode chip and said divided segment on which said diode chip is mounted.
[43" id="US-20010009301-A1-CLM-00043] 43. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein said semiconductor element is a transistor chip;
wherein, in said mounting said semiconductor element on at least one of said segments, said transistor chip is mounted on one of said plurality of segments;
wherein said method further comprises electrically coupling electrodes of said transistor chip with two of said segments adjacent said divided segment on which said transistor chip is mounted via bonding wires; and
wherein, in said disposing said resin material, said transistor chip and said bonding wires are sealed by said resin material, and said resin material fills spaces between said segments electrically coupled with said electrodes of said transistor chip and said divided segment on which said transistor chip is mounted.
[44" id="US-20010009301-A1-CLM-00044] 44. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein, in said disposing said resin material, said resin material is disposed by using a technology selected from a group consisting of molding by a metal die, coating, and potting.
[45" id="US-20010009301-A1-CLM-00045] 45. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein, in said preparing a semiconductor element, a plurality of semiconductor elements are prepared;
wherein, in said mounting said semiconductor element on at least one of said segments, said plurality of semiconductor elements are mounted on said segments; and
wherein, in said disposing said resin material, said plurality of semiconductor elements are sealed by said resin material.
[46" id="US-20010009301-A1-CLM-00046] 46. A method of manufacturing a semiconductor device as set forth in
claim 34 , wherein, in said cutting said conductive plate stuck on said supporting sheet to form a plurality of segments supported by said supporting sheet, said conductive plate is cut into lattice-like arrangement;
wherein, in said preparing a semiconductor element, a semiconductor wafer on which a plurality of semiconductor elements are formed is prepared;
wherein, in said mounting a semiconductor element on at least one of said plurality of segments, said semiconductor wafer is mounted on said plurality of segments supported by said supporting sheet, and electrodes of each semiconductor element formed on said semiconductor wafer are electrically coupled with corresponding segments of said plurality of segments via bumps;
wherein, in said disposing resin material, said resin material fills a space between said semiconductor wafer and a plurality of segments supported by said supporting sheet and spaces between respective segments of said plurality of segments; and
wherein said method further comprises cutting said semiconductor wafer and said resin material in predetermined locations to form separate semiconductor devices each including at least one semiconductor element.
[47" id="US-20010009301-A1-CLM-00047] 47. A method of manufacturing a semiconductor device comprising:
preparing a semiconductor element having electrodes on which bumps are formed;
preparing a conductive plate;
forming a first set of concave trenches in a lattice-like arrangement on the face side of said conductive plate;
forming a second set of concave trenches in a lattice-like arrangement on the backside of said conductive plate, said second set of concave trenches are shifted from said first set of concave trenches in the direction along the surface of said conductive plate;
mounting said semiconductor element on the face surface of said conductive plate, wherein electrodes of said semiconductor element are electrically coupled with segments divided by said first set of concave trenches via bumps;
filling a space between said semiconductor element and said conductive plate with resin material; and
cutting said conductive plate at locations shifted in the directions along the surface of said conductive plate from said first and second sets of concave trenches.
[48" id="US-20010009301-A1-CLM-00048] 48. A method of manufacturing a semiconductor device as set forth in
claim 47 , wherein, in said preparing a semiconductor element having electrodes on which bumps are formed, a semiconductor wafer on which a plurality of semiconductor elements are formed thereon is prepared, and each of said semiconductor element has electrodes on which bumps are formed;
wherein, in said mounting said semiconductor element on the face surface of said conductive plate, said semiconductor wafer is mounted on the face surface of said conductive plate, and electrodes of each of said semiconductor elements are electrically coupled with segments divided by said first set of concave trenches via bumps;
wherein, in said filling a space between said semiconductor element and said conductive plate with resin material, said resin material fill a space between said semiconductor wafer and said conductive plate; and
wherein said method further comprises cutting said semiconductor wafer and said resin material in predetermined locations to form separate semiconductor devices each including at least one semiconductor element.
[49" id="US-20010009301-A1-CLM-00049] 49. A method of manufacturing a semiconductor device as set forth in
claim 47 , wherein said forming a second set of concave trenches in a lattice-like arrangement on the backside of said conductive plate is performed after filling a space between said semiconductor element and said conductive plate with resin material;
wherein, in said forming a second set of concave trenches in a lattice-like arrangement on the backside of said conductive plate, said second set of concave trenches partially overlap said first set of said concave trenches and said conductive plate is separated by said first and second sets of concave trenches; and
thereby obviating said cutting said conductive plate at locations shifted in the directions along the surface of said conductive plate from said first and second sets of concave trenches.
[50" id="US-20010009301-A1-CLM-00050] 50. A method of manufacturing a semiconductor device as set forth in
claim 47 , wherein, in said forming a first set of concave trenches in a lattice-like arrangement on the face side of said conductive plate and in said forming a second set of concave trenches in a lattice-like arrangement on the backside of said conductive plate, said first and second sets of concave trenches are formed by using a technology selected from a group consisting of half-cut dicing, half-etching and press working.

类似技术:

---

公开号 | 公开日 | 专利标题

---

US6855577B2|2005-02-15|Semiconductor devices having different package sizes made by using common parts

---

US6441475B2|2002-08-27|Chip scale surface mount package for semiconductor device and process of fabricating the same

---

US7138706B2|2006-11-21|Semiconductor device and method for manufacturing the same

---

US6624523B2|2003-09-23|Structure and package of a heat spreader substrate

---

US7799611B2|2010-09-21|Partially patterned lead frames and methods of making and using the same in semiconductor packaging

---

JP4417150B2|2010-02-17|Semiconductor device

---

US6762118B2|2004-07-13|Package having array of metal pegs linked by printed circuit lines

---

EP1187202A2|2002-03-13|Semiconductor package

---

KR20050103234A|2005-10-27|Multi-die semiconductor package

---

KR20040030297A|2004-04-09|Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same

---

US8105876B2|2012-01-31|Leadframe for leadless package, structure and manufacturing method using the same

---

US6677219B2|2004-01-13|Method of forming a ball grid array package

---

US7443043B2|2008-10-28|Circuit device and method of manufacture thereof

---

US9331041B2|2016-05-03|Semiconductor device and semiconductor device manufacturing method

---

US20130017652A1|2013-01-17|Method of manufacturing a semiconductor device package with a heatsink

---

JPH11191561A|1999-07-13|Manufacture of semiconductor device

---

JP4987041B2|2012-07-25|Manufacturing method of semiconductor device

---

US6380062B1|2002-04-30|Method of fabricating semiconductor package having metal peg leads and connected by trace lines

---

JPH11191562A|1999-07-13|Manufacture of semiconductor device

---

US6160311A|2000-12-12|Enhanced heat dissipating chip scale package method and devices

---

JP2001319995A|2001-11-16|Manufacturing method of semiconductor device

---

KR100260996B1|2000-07-01|Array type semiconductor package using a lead frame and its manufacturing method

---

KR100384335B1|2003-05-16|A semiconductor packages and manufacturing method for it

---

KR20010066268A|2001-07-11|stack-type semiconductor package and method for fabricating the same

---

JP2004039679A|2004-02-05|Circuit device

同族专利:

---

公开号 | 公开日

---

US6498392B2|2002-12-24|

---

JP3420153B2|2003-06-23|

---

US20030001260A1|2003-01-02|

---

US6855577B2|2005-02-15|

---

KR100399560B1|2003-09-26|

---

KR20010083129A|2001-08-31|

---

JP2001210743A|2001-08-03|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

US20020070446A1|2000-12-13|2002-06-13|Michio Horiuchi|Semiconductor device and method for the production thereof|

---

US20030104657A1|2001-04-05|2003-06-05|Larry Kinsman|Transfer mold semiconductor packaging processes|

---

US6777788B1|2002-09-10|2004-08-17|National Semiconductor Corporation|Method and structure for applying thick solder layer onto die attach pad|

---

US20060252183A1|1999-12-27|2006-11-09|Matsushita Electric Industrial Co., Ltd.|Semiconductor device and method for the fabrication thereof|

---

US20070075404A1|2005-10-03|2007-04-05|Stats Chippac Ltd.|Integrated circuit package system with multi-surface die attach pad|

---

US20070163992A1|2003-09-06|2007-07-19|Martin Michalk|Method and device for contacting semiconductor chips|

---

US20090294932A1|2008-06-03|2009-12-03|Texas Instruments Inc.|Leadframe having delamination resistant die pad|

---

US8330270B1|1998-06-10|2012-12-11|Utac Hong Kong Limited|Integrated circuit package having a plurality of spaced apart pad portions|

---

US20130075922A1|2011-09-23|2013-03-28|Rui Huang|Integrated circuit packaging system with a substrate embedded dummy-die paddle and method of manufacture thereof|

---

US8466547B2|2009-03-30|2013-06-18|Toppan Printing Co., Ltd.|Method for manufacturing substrate for semiconductor element, and semiconductor device|

---

US20130200503A1|2012-02-08|2013-08-08|CarsemSdn, Bhd.|Protective layers in semiconductor packaging|

---

CN103280540A|2013-05-09|2013-09-04|深圳市华星光电技术有限公司|Display device and manufacturing method thereof|

---

CN103490001A|2013-07-01|2014-01-01|宁波康强电子股份有限公司|Discrete type EMC packaged LED lead frame|

---

US8742556B2|2011-01-14|2014-06-03|Toyota Jidosha Kabushiki Kaisha|Semiconductor module|

---

US8836104B2|2012-03-03|2014-09-16|Ho-Yuan Yu|Apparatus for chip thermal stress relief|

---

US8853840B2|2013-02-21|2014-10-07|Freescale Semiconductor, Inc.|Semiconductor package with inner and outer leads|

---

US8907477B2|2010-01-05|2014-12-09|Fuji Electric Co., Ltd.|Unit for semiconductor device and semiconductor device|

---

TWI471991B|2007-06-04|2015-02-01|Stats Chippac Ltd|Semiconductor packages|

---

US20150130076A1|2013-11-12|2015-05-14|Mitsubishi Electric Corporation|Semiconductor module and method for manufacturing the same|

---

EP2899672A1|2014-01-28|2015-07-29|Giesecke & Devrient GmbH|Method for producing a chip module|

---

US9287476B2|2008-09-03|2016-03-15|Nichia Corporation|Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body|

---

US9613888B2|2013-04-02|2017-04-04|Mitsubishi Electric Corporation|Semiconductor device and semiconductor module|

---

US20170154836A1|2015-11-27|2017-06-01|Fuji Electric Co., Ltd.|Semiconductor device|

---

US10586771B2|2013-12-16|2020-03-10|Utac Headquarters Pte, Ltd|Conductive shield for semiconductor package|US4884124A|1986-08-19|1989-11-28|Mitsubishi Denki Kabushiki Kaisha|Resin-encapsulated semiconductor device|

---

JPS6422474A|1987-07-15|1989-01-25|Plasma Uerudoshiya Kk|Seam welding machine|

---

JPH01106456A|1987-10-19|1989-04-24|Matsushita Electric Ind Co Ltd|Semiconductor integrated circuit device|

---

US5200362A|1989-09-06|1993-04-06|Motorola, Inc.|Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film|

---

US5225373A|1990-03-07|1993-07-06|Mitsubishi Denki Kabushiki Kaisha|Method of manufacturing semiconductor pressure sensor device with two semiconductor pressure sensor chips|

---

DE69227937T2|1991-02-12|1999-05-12|Matsushita Electronics Corp|Lead frames and resin sealed semiconductor device therefor|

---

JPH05129473A|1991-11-06|1993-05-25|Sony Corp|Resin-sealed surface-mounting semiconductor device|

---

EP0602298B1|1992-12-15|1998-06-10|STMicroelectronics S.r.l.|Support for a semiconductor package|

---

JP3522403B2|1994-08-24|2004-04-26|富士通株式会社|Semiconductor device|

---

JPH08115989A|1994-08-24|1996-05-07|Fujitsu Ltd|Semiconductor device and its manufacture|

---

JP3007833B2|1995-12-12|2000-02-07|富士通株式会社|Semiconductor device and its manufacturing method, lead frame and its manufacturing method|

---

JPH09252014A|1996-03-15|1997-09-22|Nissan Motor Co Ltd|Manufacturing method of semiconductor element|

---

JP2899956B2|1996-05-01|1999-06-02|東洋精密工業株式会社|Semiconductor device and manufacturing method thereof|

---

JP3292082B2|1997-03-10|2002-06-17|松下電器産業株式会社|Terminal land frame and method of manufacturing resin-encapsulated semiconductor device using the same|

---

JPH10270496A|1997-03-27|1998-10-09|Hitachi Ltd|Electronic device, information processor, semiconductor device, semiconductor chip, and mounting method thereof|

---

JPH11121646A|1997-10-14|1999-04-30|Hitachi Cable Ltd|Semiconductor package and manufacture thereof|

---

JPH11312749A|1998-02-25|1999-11-09|Fujitsu Ltd|Semiconductor device, its manufacture and manufacture of lead frame|

---

JP2986788B1|1998-10-21|1999-12-06|松下電子工業株式会社|Resin-sealed semiconductor device and method of manufacturing the same|

---

JP3436159B2|1998-11-11|2003-08-11|松下電器産業株式会社|Method for manufacturing resin-encapsulated semiconductor device|

---

JP3215686B2|1999-08-25|2001-10-09|株式会社日立製作所|Semiconductor device and manufacturing method thereof|

---

TW445608B|2000-05-19|2001-07-11|Siliconware Precision Industries Co Ltd|Semiconductor package and manufacturing method thereof of lead frame without flashing|

---

CN1265451C|2000-09-06|2006-07-19|三洋电机株式会社|Semiconductor device and manufactoring method thereof|US6143981A|1998-06-24|2000-11-07|Amkor Technology, Inc.|Plastic integrated circuit package and method and leadframe for making the package|

---

US7042068B2|2000-04-27|2006-05-09|Amkor Technology, Inc.|Leadframe and semiconductor package made using the leadframe|

---

US6661083B2|2001-02-27|2003-12-09|Chippac, Inc|Plastic semiconductor package|

---

US6545345B1|2001-03-20|2003-04-08|Amkor Technology, Inc.|Mounting for a package containing a chip|

---

KR100369393B1|2001-03-27|2003-02-05|앰코 테크놀로지 코리아 주식회사|Lead frame and semiconductor package using it and its manufacturing method|

---

KR100677651B1|2001-04-13|2007-02-01|야마하 가부시키가이샤|Semiconductor device and package, and method of manufacture therefor|

---

JP4503632B2|2001-05-11|2010-07-14|株式会社ルネサステクノロジ|Manufacturing method of semiconductor device|

---

JP4023159B2|2001-07-31|2007-12-19|ソニー株式会社|Manufacturing method of semiconductor device and manufacturing method of laminated semiconductor device|

---

JP4679000B2|2001-07-31|2011-04-27|三洋電機株式会社|Plate|

---

US7001798B2|2001-11-14|2006-02-21|Oki Electric Industry Co., Ltd.|Method of manufacturing semiconductor device|

---

DE10148042B4|2001-09-28|2006-11-09|Infineon Technologies Ag|Electronic component with a plastic housing and components of a height-structured metallic system carrier and method for their production|

---

US6750546B1|2001-11-05|2004-06-15|Skyworks Solutions, Inc.|Flip-chip leadframe package|

---

US20050012225A1|2002-11-15|2005-01-20|Choi Seung-Yong|Wafer-level chip scale package and method for fabricating and using the same|

---

JP3938525B2|2002-07-24|2007-06-27|株式会社ルネサステクノロジ|Manufacturing method of semiconductor device|

---

JP2004063615A|2002-07-26|2004-02-26|Nitto Denko Corp|Semiconductor device, manufacturing method thereof and adhesive sheet for manufacturing the same|

---

US7061077B2|2002-08-30|2006-06-13|Fairchild Semiconductor Corporation|Substrate based unmolded package including lead frame structure and semiconductor die|

---

US6905914B1|2002-11-08|2005-06-14|Amkor Technology, Inc.|Wafer level package and fabrication method|

---

US7723210B2|2002-11-08|2010-05-25|Amkor Technology, Inc.|Direct-write wafer level chip scale package|

---

US6930377B1|2002-12-04|2005-08-16|National Semiconductor Corporation|Using adhesive materials as insulation coatings for leadless lead frame semiconductor packages|

---

JP4328520B2|2002-12-06|2009-09-09|日本電気株式会社|Semiconductor device and manufacturing method thereof|

---

JP3748849B2|2002-12-06|2006-02-22|三菱電機株式会社|Resin-sealed semiconductor device|

---

US6798047B1|2002-12-26|2004-09-28|Amkor Technology, Inc.|Pre-molded leadframe|

---

JP3666749B2|2003-01-07|2005-06-29|沖電気工業株式会社|Semiconductor device|

---

JP4245370B2|2003-02-21|2009-03-25|大日本印刷株式会社|Manufacturing method of semiconductor device|

---

JP3952963B2|2003-02-21|2007-08-01|ヤマハ株式会社|Semiconductor device and manufacturing method thereof|

---

US6750545B1|2003-02-28|2004-06-15|Amkor Technology, Inc.|Semiconductor package capable of die stacking|

---

US6794740B1|2003-03-13|2004-09-21|Amkor Technology, Inc.|Leadframe package for semiconductor devices|

---

US6683370B1|2003-04-15|2004-01-27|Motorola, Inc.|Semiconductor component and method of manufacturing same|

---

US7049683B1|2003-07-19|2006-05-23|Ns Electronics BangkokLtd.|Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound|

---

JP4397653B2|2003-08-26|2010-01-13|日東電工株式会社|Adhesive sheet for semiconductor device manufacturing|

---

JP2005109225A|2003-09-30|2005-04-21|Sanyo Electric Co Ltd|Circuit device|

---

US7138707B1|2003-10-21|2006-11-21|Amkor Technology, Inc.|Semiconductor package including leads and conductive posts for providing increased functionality|

---

JP3910598B2|2004-03-04|2007-04-25|松下電器産業株式会社|Resin-sealed semiconductor device and manufacturing method thereof|

---

JP2005327830A|2004-05-13|2005-11-24|Mitsubishi Electric Corp|Semiconductor micro device|

---

US7943427B2|2004-07-15|2011-05-17|Dai Nippon Printing Co., Ltd.|Semiconductor device, substrate for producing semiconductor device and method of producing them|

---

WO2006009029A1|2004-07-15|2006-01-26|Dai Nippon Printing Co., Ltd.|Semiconductor device and semiconductor device producing substrate and production method for semiconductor device producing substrate|

---

KR101070897B1|2004-07-22|2011-10-06|삼성테크윈 주식회사|Printed circuit board having structure for relieving stress concentration, and semiconductor chip package equiped with it|

---

WO2006059381A1|2004-12-01|2006-06-08|Renesas Technology Corp.|Semiconductor device and method for manufacturing the same|

---

WO2006132130A1|2005-06-06|2006-12-14|Rohm Co., Ltd.|Semiconductor device, substrate and semiconductor device manufacturing method|

---

JP4679991B2|2005-07-26|2011-05-11|ルネサスエレクトロニクス株式会社|Semiconductor device|

---

US7274089B2|2005-09-19|2007-09-25|Stats Chippac Ltd.|Integrated circuit package system with adhesive restraint|

---

US7947535B2|2005-10-22|2011-05-24|Stats Chippac Ltd.|Thin package system with external terminals|

---

US7507603B1|2005-12-02|2009-03-24|Amkor Technology, Inc.|Etch singulated semiconductor package|

---

US7572681B1|2005-12-08|2009-08-11|Amkor Technology, Inc.|Embedded electronic component package|

---

US20070132075A1|2005-12-12|2007-06-14|Mutsumi Masumoto|Structure and method for thin single or multichip semiconductor QFN packages|

---

KR100755658B1|2006-03-09|2007-09-04|삼성전기주식회사|Light emitting diode package|

---

US7759782B2|2006-04-07|2010-07-20|Tessera, Inc.|Substrate for a microelectronic package and method of fabricating thereof|

---

US7902660B1|2006-05-24|2011-03-08|Amkor Technology, Inc.|Substrate for semiconductor device and manufacturing method thereof|

---

US7968998B1|2006-06-21|2011-06-28|Amkor Technology, Inc.|Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package|

---

JP2008034567A|2006-07-27|2008-02-14|Fujitsu Ltd|Semiconductor device and manufacturing method therefor|

---

US20080079127A1|2006-10-03|2008-04-03|Texas Instruments Incorporated|Pin Array No Lead Package and Assembly Method Thereof|

---

US7687893B2|2006-12-27|2010-03-30|Amkor Technology, Inc.|Semiconductor package having leadframe with exposed anchor pads|

---

US7829990B1|2007-01-18|2010-11-09|Amkor Technology, Inc.|Stackable semiconductor package including laminate interposer|

---

JP4270282B2|2007-01-23|2009-05-27|セイコーエプソン株式会社|Manufacturing method of semiconductor device|

---

US7982297B1|2007-03-06|2011-07-19|Amkor Technology, Inc.|Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same|

---

TWI337387B|2007-04-20|2011-02-11|Chipmos Technologies Inc|Leadframe for leadless package, package structure and manufacturing method using the same|

---

US20080284038A1|2007-05-16|2008-11-20|Dimaano Jr Antonio B|Integrated circuit package system with perimeter paddle|

---

US7977774B2|2007-07-10|2011-07-12|Amkor Technology, Inc.|Fusion quad flat semiconductor package|

---

US7767497B2|2007-07-12|2010-08-03|Tessera, Inc.|Microelectronic package element and method of fabricating thereof|

---

US7807498B2|2007-07-31|2010-10-05|Seiko Epson Corporation|Substrate, substrate fabrication, semiconductor device, and semiconductor device fabrication|

---

US7875988B2|2007-07-31|2011-01-25|Seiko Epson Corporation|Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same|

---

US7687899B1|2007-08-07|2010-03-30|Amkor Technology, Inc.|Dual laminate package structure with embedded elements|

---

DE102007044620A1|2007-09-19|2009-04-16|Semikron Elektronik Gmbh & Co. Kg|Arrangement with a connection device and at least one semiconductor component|

---

US7915716B2|2007-09-27|2011-03-29|Stats Chippac Ltd.|Integrated circuit package system with leadframe array|

---

US7777351B1|2007-10-01|2010-08-17|Amkor Technology, Inc.|Thin stacked interposer package|

---

US8089159B1|2007-10-03|2012-01-03|Amkor Technology, Inc.|Semiconductor package with increased I/O density and method of making the same|

---

US7847386B1|2007-11-05|2010-12-07|Amkor Technology, Inc.|Reduced size stacked semiconductor package and method of making the same|

---

US8957515B2|2007-11-07|2015-02-17|Stats Chippac Ltd.|Integrated circuit package system with array of external interconnects|

---

US20090152683A1|2007-12-18|2009-06-18|National Semiconductor Corporation|Rounded die configuration for stress minimization and enhanced thermo-mechanical reliability|

---

US7808089B2|2007-12-18|2010-10-05|National Semiconductor Corporation|Leadframe having die attach pad with delamination and crack-arresting features|

---

US7956453B1|2008-01-16|2011-06-07|Amkor Technology, Inc.|Semiconductor package with patterning layer and method of making same|

---

US7723852B1|2008-01-21|2010-05-25|Amkor Technology, Inc.|Stacked semiconductor package and method of making same|

---

US7732901B2|2008-03-18|2010-06-08|Stats Chippac Ltd.|Integrated circuit package system with isloated leads|

---

JP4483969B2|2008-03-31|2010-06-16|セイコーエプソン株式会社|Substrate, manufacturing method thereof, and manufacturing method of semiconductor device|

---

US8067821B1|2008-04-10|2011-11-29|Amkor Technology, Inc.|Flat semiconductor package with half package molding|

---

US7768135B1|2008-04-17|2010-08-03|Amkor Technology, Inc.|Semiconductor package with fast power-up cycle and method of making same|

---

US7517726B1|2008-04-25|2009-04-14|Shanghai Kaihong Technology Co., Ltd|Wire bonded chip scale package fabrication methods|

---

US7808084B1|2008-05-06|2010-10-05|Amkor Technology, Inc.|Semiconductor package with half-etched locking features|

---

JP4821803B2|2008-05-23|2011-11-24|セイコーエプソン株式会社|Semiconductor device and manufacturing method of semiconductor device|

---

US8125064B1|2008-07-28|2012-02-28|Amkor Technology, Inc.|Increased I/O semiconductor package and method of making same|

---

US8184453B1|2008-07-31|2012-05-22|Amkor Technology, Inc.|Increased capacity semiconductor package|

---

US7964448B2|2008-09-18|2011-06-21|Infineon Technologies Ag|Electronic device and method of manufacturing same|

---

US7847392B1|2008-09-30|2010-12-07|Amkor Technology, Inc.|Semiconductor device including leadframe with increased I/O|

---

US7989933B1|2008-10-06|2011-08-02|Amkor Technology, Inc.|Increased I/O leadframe and semiconductor device including same|

---

US8008758B1|2008-10-27|2011-08-30|Amkor Technology, Inc.|Semiconductor device with increased I/O leadframe|

---

JP5432918B2|2008-10-31|2014-03-05|太陽誘電株式会社|Manufacturing method of printed wiring board|

---

US8089145B1|2008-11-17|2012-01-03|Amkor Technology, Inc.|Semiconductor device including increased capacity leadframe|

---

US8072050B1|2008-11-18|2011-12-06|Amkor Technology, Inc.|Semiconductor device with increased I/O leadframe including passive device|

---

US7875963B1|2008-11-21|2011-01-25|Amkor Technology, Inc.|Semiconductor device including leadframe having power bars and increased I/O|

---

US7982298B1|2008-12-03|2011-07-19|Amkor Technology, Inc.|Package in package semiconductor device|

---

US8487420B1|2008-12-08|2013-07-16|Amkor Technology, Inc.|Package in package semiconductor device with film over wire|

---

US8680656B1|2009-01-05|2014-03-25|Amkor Technology, Inc.|Leadframe structure for concentrated photovoltaic receiver package|

---

US20170117214A1|2009-01-05|2017-04-27|Amkor Technology, Inc.|Semiconductor device with through-mold via|

---

US8058715B1|2009-01-09|2011-11-15|Amkor Technology, Inc.|Package in package device for RF transceiver module|

---

JP5131206B2|2009-01-13|2013-01-30|セイコーエプソン株式会社|Semiconductor device|

---

US8026589B1|2009-02-23|2011-09-27|Amkor Technology, Inc.|Reduced profile stackable semiconductor package|

---

US7960818B1|2009-03-04|2011-06-14|Amkor Technology, Inc.|Conformal shield on punch QFN semiconductor package|

---

US8575742B1|2009-04-06|2013-11-05|Amkor Technology, Inc.|Semiconductor device with increased I/O leadframe including power bars|

---

JP2010283147A|2009-06-04|2010-12-16|Seiko Epson Corp|Method for manufacturing semiconductor device, method for manufacturing substrate, and the substrate|

---

US8796561B1|2009-10-05|2014-08-05|Amkor Technology, Inc.|Fan out build up substrate stackable package and method|

---

TWI381467B|2009-10-27|2013-01-01|Powertech Technology Inc|Fabrication method for chip package structure with high pin count|

---

US8937381B1|2009-12-03|2015-01-20|Amkor Technology, Inc.|Thin stackable package and method|

---

US9691734B1|2009-12-07|2017-06-27|Amkor Technology, Inc.|Method of forming a plurality of electronic component packages|

---

US8324511B1|2010-04-06|2012-12-04|Amkor Technology, Inc.|Through via nub reveal method and structure|

---

JP5432045B2|2010-04-13|2014-03-05|シチズン電子株式会社|Manufacturing method of semiconductor light emitting device|

---

US8294276B1|2010-05-27|2012-10-23|Amkor Technology, Inc.|Semiconductor device and fabricating method thereof|

---

US8440554B1|2010-08-02|2013-05-14|Amkor Technology, Inc.|Through via connected backside embedded circuit features structure and method|

---

US8487445B1|2010-10-05|2013-07-16|Amkor Technology, Inc.|Semiconductor device having through electrodes protruding from dielectric layer|

---

US8791501B1|2010-12-03|2014-07-29|Amkor Technology, Inc.|Integrated passive device structure and method|

---

US8674485B1|2010-12-08|2014-03-18|Amkor Technology, Inc.|Semiconductor device including leadframe with downsets|

---

US8390130B1|2011-01-06|2013-03-05|Amkor Technology, Inc.|Through via recessed reveal structure and method|

---

US8648450B1|2011-01-27|2014-02-11|Amkor Technology, Inc.|Semiconductor device including leadframe with a combination of leads and lands|

---

US8766100B2|2011-03-02|2014-07-01|Samsung Electronics Co., Ltd.|Printed circuit board and semiconductor package using the same|

---

US9287191B2|2011-10-12|2016-03-15|Taiwan Semiconductor Manufacturing Company, Ltd.|Semiconductor device package and method|

---

CN102376671A|2011-11-29|2012-03-14|杭州矽力杰半导体技术有限公司|Lead frame and flip-chip type semiconductor packaging structure using the same|

---

US8552548B1|2011-11-29|2013-10-08|Amkor Technology, Inc.|Conductive pad on protruding through electrode semiconductor device|

---

US9704725B1|2012-03-06|2017-07-11|Amkor Technology, Inc.|Semiconductor device with leadframe configured to facilitate reduced burr formation|

---

US9048298B1|2012-03-29|2015-06-02|Amkor Technology, Inc.|Backside warpage control structure and fabrication method|

---

US9129943B1|2012-03-29|2015-09-08|Amkor Technology, Inc.|Embedded component package and fabrication method|

---

US8723338B2|2012-08-15|2014-05-13|Stats Chippac Ltd.|Integrated circuit packaging system with array contacts and method of manufacture thereof|

---

KR20140115021A|2013-03-20|2014-09-30|에스케이하이닉스 주식회사|Semiconductor package and method for fabricating the same|

---

US9673122B2|2014-05-02|2017-06-06|Amkor Technology, Inc.|Micro lead frame structure having reinforcing portions and method|

---

KR101486790B1|2013-05-02|2015-01-28|앰코 테크놀로지 코리아 주식회사|Micro Lead Frame for semiconductor package|

---

KR101563911B1|2013-10-24|2015-10-28|앰코 테크놀로지 코리아 주식회사|Semiconductor package|

---

KR20150053579A|2013-11-08|2015-05-18|삼성전기주식회사|Electric component module and manufacturing method threrof|

---

US9646917B2|2014-05-29|2017-05-09|Invensas Corporation|Low CTE component with wire bond interconnects|

---

TWI557183B|2015-12-16|2016-11-11|財團法人工業技術研究院|Siloxane resin composition, and photoelectric device employing the same|

---

JP2018046057A|2016-09-12|2018-03-22|株式会社東芝|Semiconductor package|

---

WO2019207664A1|2018-04-25|2019-10-31|三菱電機株式会社|Shared base plate and semiconductor module provided with same|

法律状态:
2001-01-23| AS| Assignment|Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AZUMA, KOSUKE;REEL/FRAME:011476/0336 Effective date: 20010112 |

---

2003-02-19| AS| Assignment|Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013736/0321 Effective date: 20021101 |

---

2004-07-06| CC| Certificate of correction|

---

2006-06-05| FPAY| Fee payment|Year of fee payment: 4 |

---

2010-05-27| FPAY| Fee payment|Year of fee payment: 8 |

---

2010-11-18| AS| Assignment|Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025375/0918 Effective date: 20100401 |

---

2014-08-01| REMI| Maintenance fee reminder mailed|

---

2014-12-24| LAPS| Lapse for failure to pay maintenance fees|

---

2015-01-19| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |

---

2015-02-10| FP| Lapsed due to failure to pay maintenance fee|Effective date: 20141224 |

优先权:

---

申请号 | 申请日 | 专利标题

---

JP2000013794A|JP3420153B2|2000-01-24|2000-01-24|Semiconductor device and manufacturing method thereof|

---

JP2000-013794||2000-01-24||US10/234,019| US6855577B2|2000-01-24|2002-09-03|Semiconductor devices having different package sizes made by using common parts|